CY14E256L-SZ35XIT

CY14E256L 256 Kbit (32K x 8) nvSRAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The Cypress CY14E256L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. 25 ns, 35 ns, and 45 ns Access Times Pin Compatible with STK14C88 Hands Off Automatic STORE on Power Down with External 68 µF Capacitor STORE to QuantumTrap Nonvolatile Elements is Initiated by Software, Hardware, or AutoStore on Power Down RECALL to SRAM Initiated by Software or Power Up Unlimited READ, WRITE, and RECALL Cycles 1,000,000 STORE Cycles to QuantumTrap 100 Year Data Retention to QuantumTrap Single 5V+10% Operation Commercial and Industrial Temperature 32-pin SOIC Package (RoHS Compliance) CDIP (300 mil) Package Logic Block Diagram Quantum Trap 512 X 512 A5 A6 A7 A8 A9 A 11 A 12 A 13 A 14 V CC V CAP STORE POWER CONTROL STORE/ RECALL CONTROL ROW DECODER STATIC RAM ARRAY 512 X 512 RECALL HSB SOFTWARE DETECT COLUMN I/O A13 - A 0 DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFERS DQ 1 COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 OE CE WE Cypress Semiconductor Corporation Document Number: 001-06968 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 18, 2009 [+] Feedback CY14E256L Pin Configurations Figure 1. Pin Diagram: 32-Pin SOIC/DIP Table 1. Pin Definitions Pin Name A0–A14 DQ0-DQ7 WE CE OE VSS VCC HSB VCAP W E G Alt I/O Type Input Input Input Input Ground Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Ground for the Device. The device is connected to ground of the system. Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. Power Supply Power Supply Inputs to the Device. Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Document Number: 001-06968 Rev. *G Page 2 of 18 [+] Feedback CY14E256L Device Operation The CY14E256L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY14E256L supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. having a capacitor of between 68 uF and 220 uF (+ 20%) rated at 6V should be provided. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up. Figure 2. AutoStore Mode SRAM Read The CY14E256L performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 μF capacitor. In this mode, the AutoStore function of the CY14E256L operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms STORE cycle. To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored, unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 2.2 ohm resistor should be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP. AutoStore Operation The CY14E256L stores data to nvSRAM using one of three storage operations: 1. Hardware store activated by HSB 2. Software store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E256L. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor AutoStore Inhibit mode If an automatic STORE on power loss is not required, then VCC is tied to ground and + 5V is applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the CY14E256L is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control or the HSB pin. To enable or disable Autostore using an I/O port pin see “Preventing Store” on page 5. It is not permissible to change between these three options ”on the fly”. Document Number: 001-06968 Rev. *G Page 3 of 18 [+] Feedback CY14E256L Figure 3. AutoStore Inhibit Mode If the CY14E256L is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14E256L software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation. Hardware STORE (HSB) Operation The CY14E256L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14E256L conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver. SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14E256L continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the CY14E256L continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY14E256L remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. Hardware RECALL (Power Up) During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. Document Number: 001-06968 Rev. *G Page 4 of 18 [+] Feedback CY14E256L Data Protection The CY14E256L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14E256L is in a WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions. Figure 4. Current Versus Cycle Time (READ) Noise Considerations The CY14E256L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. Hardware Protect The CY14E256L offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage conditions. When VCAP 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VCC 4.5V to 5.5V 4.5V to 5.5V DC Electrical Characteristics Parameter ICC1 Description Average VCC Current Over the operating range (VCC = 4.5V to 5.5V) [6] Test Conditions Commercial tRC = 25 ns tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Industrial Values obtained without output loads. IOUT = 0 mA. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE WE > (VCC – 0.2V). All other inputs cycling. Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. tRC = 25 ns, CE > VIH tRC = 35 ns, CE > VIH tRC = 45 ns, CE > VIH Commercial Min Max 97 80 70 100 85 70 3 10 Unit mA mA mA mA mA mA mA ICC2 ICC3 Average VCC Current during STORE Average VCC Current at tRC= 200 ns, 5V, 25°C Typical Average VCAP Current during AutoStore Cycle VCC Standby Current ICC4 ISB [7] ISB1[7] 2 1.5 mA mA VCC Standby Current (Standby, Cycling TTL Input Levels) 30 25 22 31 26 23 -1 -5 2.2 +1 +5 VCC + 0.5 mA mA mA mA mA mA μA μA V Industrial IIX IOZ VIH Input Leakage Current Off State Output Leakage Current Input HIGH Voltage VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL Notes 6. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 7. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-06968 Rev. *G Page 7 of 18 [+] Feedback CY14E256L DC Electrical Characteristics Parameter VIL VOH VOL VBL VCAP Description Input LOW Voltage Output HIGH Voltage Output LOW Voltage Logic ‘0’ Voltage on HSB Output Storage Capacitor IOUT = –4 mA IOUT = 8 mA IOUT = 3 mA Between VCAP pin and Vss, 6V rated. 68 µF +20% nom. 54 Over the operating range (continued)(VCC = 4.5V to 5.5V) [6] Test Conditions Min VSS – 0.5 2.4 0.4 0.4 260 Max 0.8 Unit V V V V uF Data Retention and Endurance Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 100 1,000 Unit Years K Capacitance Parameter CIN COUT In the following table, the capacitance parameters are listed.[8] Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Max 5 7 Unit pF pF Thermal Resistance Parameter In the following table, the thermal resistance parameters are listed.[8] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 32-SOIC 35.45 13.26 32-CDIP TBD TBD Unit °C/W °C/W ΘJA ΘJC Figure 6. AC Test Loads R1 963Ω 5.0V Output 30 pF R2 512Ω Output 5 pF R2 512Ω 5.0V R1 963Ω For Tri-state Specs AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% - 90%)........................