CY2212ZXC-2

THIS SPEC IS OBSOLETE Spec No: 38-07466 Spec Title: CY2212 DIRECT RAMBUS CLOCK GENERATOR (LITE) Sunset Owner: Christopher Martin (CXQ) Replaced by: NONE CY2212 Direct Rambus Clock Generator (Lite) Features Benefits ■ Direct Rambus Clock Support ■ One pair of differential output drivers ■ High Speed Clock Support ■ 400 MHz and 300 MHz differential output frequencies ■ Input Select Option ■ Phase Locked Loop (PLL) multiplier select ■ Crystal Oscillator Divider Output ■ LCLK = XTAL/2, not driven by PLL ■ Output Edge Rate Control ■ Minimize EMI ■ 16-Pin TSSOP ■ Space saving, low cost package Logic Block Diagram Xtal PLL CLK Oscillator xM CLKB XIN XOUT S /2 LCLK Crystal Value = 18.75 MHz Pinouts Figure 1. Pin Configuration – 16-Pin TSSOP Package 16-pin TSSOP TOP VIEW 1 16 S VSSP 2 15 VDD XOUT 3 14 VSS XIN 4 13 CLK VDDL 5 12 CLKB LCLK 6 11 VSS VSSL 7 10 VDD NC 8 CY2212 VDDP 9 NC Table 1. Frequency Select Table S M (PLL Multiplier) CLK, CLKB LCLK 0 16 300 MHz 9.375 MHz 1 64/3 400 MHz 9.375 MHz Cypress Semiconductor Corporation Document Number : 38-07466 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 7, 2010 [+] Feedback CY2212 Table 2. Pin Description Pin Name Pin Number Description VDDP 1 3.3V Power Supply for PLL VSSP 2 Ground for PLL XOUT 3 Reference Crystal Feedback XIN 4 Reference Crystal Input VDDL 5 1.8V Power Supply for LCLK LCLK 6 LVCMOS Output, x1/2 Crystal Frequency VSSL 7 Ground for LCLK NC 8 No Connect (Reserved for Test Mode) NC 9 No Connect (Reserved for Test Mode) VDD 10 3.3V Power Supply VSS 11 Ground CLKB 12 Output Clock (complement), Connect to Rambus Channel CLK 13 Output Clock, Connect to Rambus Channel VSS 14 Ground VDD 15 3.3V Power Supply S 16 PLL Multiplier Select Input, Pull-up Resistor Internal Absolute Maximum Conditions Parameter Min Max Unit Max voltage on VDD, VDDP, or VDDL with respect to ground –0.5 4.0 V VI, ABS Max voltage on any pin with respect to ground –0.5 VDD + 0.5 V VIL, ABS Max voltage on LCLK with respect to ground –0.5 VDDL + 0.5 V VDD,ABS Description Crystal Requirements These are the requirements for the recommended crystal to be used with the CY2212 DRCG Lite clock source. The crystal load capacitance is internally set to 11 pF. Crystal Requirements Parameter Description XF Frequency XFTOL Frequency Tolerance[1] XEQRES Equivalent Min Max Unit 14.0625 18.75 MHz –15 15 ppm 100  Resistance[2] Drift[3] XTEMP Temperature 10 ppm XDRIVE Drive Level 0.01 1500 W XMI Motional Inductance 20.7 25.3 mH XIR Insulation Resistance 500 M XSAR Spurious Attenuation Ratio[4] 3 dB XOS Overtone Spurious 8 dB Notes 1. At 25°C ± 3°C. 2. CL = 10 pF. 3. –10°C to 75°C. 4. At XF ± 500 kHz. Document Number : 38-07466 Rev. *C Page 2 of 13 [+] Feedback CY2212 DC Electrical Specification Parameter Description Min Max Unit VDD Supply Voltage 3.04 3.56 V VDDL LCLK Supply Voltage 1.7 2.1 V TA Ambient Operating Temperature 0 70 °C VIL Input Signal Low Voltage At Pin S – 0.35 VDD VIH Input Signal High Voltage At Pin S 0.65 – VDD RPUP Internal Pull Up Resistance 10 100 k AC Electrical Specifications Parameter fXTAL,IN Description [5] Input Frequency at Crystal Input [6] Min Typ Max Unit 14.0625 – 18.75 MHz CIN,CMOS Input Capacitance at S Pin – – 10 pF CXTAL Crystal Load Capacitance – 11 – pF Notes 5. Nominal condition with 18.75 MHz crystal. 6. Capacitance measured at Freq = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV. Document Number : 38-07466 Rev. *C Page 3 of 13 [+] Feedback CY2212 DC Device Specifications Parameter Description Min Max Unit VCM Differential Output Common Mode Voltage 1.35 1.75 V VX Differential Output Crossing Point Voltage 1.25 1.85 V VCOS Output Voltage Swing (P-P Single-Ended)[7] 0.4 0.7 V VCOH Output High Voltage – 2.1 V VCOL Output Low Voltage 1.0 – V 12 50  VDDL – 0.45V VDDL V 0 0.45 V [8] rOUT Output Dynamic Resistance (at Pins) VLOH LCLK Output High Voltage at IOH = –10 mA VLOL LCLK Output Low Voltage at IOL = 10 mA State Transition Characteristics Specifies the maximum settling time of the CLK, CLKB, and LCLK outputs from device power up. For VDD, VDDP, and VDDL any sequences are allowed to power up and power down the CY2212 DRCG Lite. State Transition Characteristics From VDD/VDDL/VDDP On To CLK/CLKB/LCLK Normal Transition Latency 3 ms Description Time from VDD/VDDL/VDDP is applied and settled to CLK/CLKB/LCLK outputs settled. Notes 7. VCOS = VOH – VOL. 8. rOUT =  VO/ IO. This is defined at the output pins, not at the measurement point of Figure 4. Document Number : 38-07466 Rev. *C Page 4 of 13 [+] Feedback CY2212 AC Device Specifications Parameter tCYCLE tJ tJL DC tDC,ERR Description Clock Cycle Time Min Max Unit 2.5 3.33 ns Jitter Over 1–6 Clock Cycles at 400 MHz[9] – 100 ps Jitter Over 1–6 Clock Cycles at 300 MHz[9] – 140 ps Long-Term Jitter at 400 MHz – 300 ps Long-Term Jitter at 300 MHz – 400 ps 45% 55% tCYCLE Cycle-Cycle Duty Cycle Error at 400 MHz – 50 ps Cycle-Cycle Duty Cycle Error at 300 MHz – 70 ps 250 500 ps – 100 ps 50 kHz (–3 dB) 8 MHz (–20 dB) 106.6 142.2 ns Long-Term Average Output Duty Cycle tCR, tCF Output Rise and Fall Times (Measured at 20%–80% of oUtput Voltage) tCR, CF Difference Between Output Rise and Fall Times on the Same Pin of a Single Device (20%–80%) BWLOOP PLL Loop Bandwidth tCYCLE,L LCLK Clock Cycle Time tLR, tLF LCLK Output Rise and Fall Time – 1 ns tJC,L Jitter[10] –0.8 0.8 ns LCLK Cycle Jitter[10, 11] tJ10,L LCLK 10-Cycle DCL LCLK Output Duty Cycle –1.1 * tJC,L 1.1 * tJC,L 40% 60% ns tCYCLE,L Notes 9. Output short-term jitter specification is peak-peak and defined in Figure 11. 10. LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period as defined on page 11. 11. LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter as defined on page 11. Document Number : 38-07466 Rev. *C Page 5 of 13 [+] Feedback CY2212 Functional Specifications This section gives the detailed functional specifications of the device physical layer. These specifications refer to the logical and physical interfaces. Crystal Input The CY2212 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 4 of this datasheet. Select Input There is only one select input, pin S. This pin selects the frequency multiplier in the PLL, and is a standard LVCMOS input. The S pin has an internal pull up resistor. The multiplier selection is given on Frequency Select Table on page 1 of this datasheet. LCLK Output Driver In addition to the Rambus clock driver outputs, there is another clock output driver. The LCLK driver is a standard LVCMOS output driver. Figure 2 below shows the LCLK output driver load circuit. Figure 2. LCLK Test Load Circuit 120 10 pF Figure 3 shows the clock driver equivalent circuit. Figure 3. Equivalent Circuit RP(RS + ROUT)/(RP + RS + ROUT). Measurement Point RT = ZCH Differential Driver The clock driver is specified as a black-box at the packaged pins. The output characteristics are measured after the series resistance, RS. The outputs are terminated differentially, with no applied termination voltage. As mentioned previously, the clock driver’s output impedance matches the channel impedance. To accomplish this, each of the output driver devices are sized to have an ROUT of about 20  when fully turned on. ROUT is the dynamic output resistance, and is defined in the DC Device Specifications table on page 4 of this datasheet. Since ROUT is in series with RS, and that combination is in parallel with RP, the effective output impedance is given by: RSL Clock Output Driver RS The output clocks drive transmission lines, potentially long lines. Since circuit board traces act as lossy, imperfectly terminated transmission lines with some discontinuities, there are reflections generated that travel back to the DRCG Lite output driver. If the output impedance does not match ZCH, secondary reflections are generated that add to position dependent timing uncertainty. Therefore, the CY2212 not only provides proper output voltage swings, but also provides a well-matched output impedance. The driver impedance, ROUT, is in series with RS, and the combination is in parallel with RP. Figure 4 shows the clock driver implemented as a push-pull driver. When stimulating the output driver, the transmission lines shown in Figure 4 can be replaced by a direct connection to the termination resistors, RT. The values for the external components are given in Table 1. 120 LCLK on the channel. The nominal value of the channel impedance, ZCH, is 28 . Series resistor RS and parallel resistor RP are used to set the voltage swing on the channel. The driver output characteristics are defined together with the external components, and the output clock is specified at the measurement point indicated in Figure 3. The complete set of external components for the output driver, including edge-rate filter capacitors required for system operation, are shown in Figure 4. The values for the external components are given in Table 1. RP ZCH RP RSS ZCH RT = ZCH Measurement Point The differential driver has a low output impedance in the range of about 20 . The driver also produces a specified voltage swing Document Number : 38-07466 Rev. *C This calculation results in an effective output impedance of about 27  for the values listed in Table 1. Since the total impedance is dominated by the external resistors, a large possible range of ROUT is allowed. When the output is transitioning, the impedance of the CMOS devices increases dramatically. The purpose of RP is to limit the maximum output impedance during output transitions. In order to control signal attenuation and EMI, clock signal rise/fall times must be tightly controlled. Therefore, external filter capacitors CF are used to control the output slew rate. In addition, the capacitor CMID is used to provide AC ground at the mid-point of the RP resistors. Table 1 gives the nominal values of the external components and their maximum acceptable tolerance, assuming ZCH = 28 . Page 6 of 13 [+] Feedback CY2212 Figure 4. Output Driver CF RS DRCG Lite Measurement Point RT =ZCH RP CMID ZCH RP RS CF CMID RT =ZCH ZCH Measurement Point Table 3. Output External Component Values Parameter Description Value Tolerance Unit RS Series Resistor 68 ±5%  RP Parallel Resistor 39 ±5%  CF Edge-rate Filter Capacitor 15 ±10% pF 0.01 ±20% F CMID AC Ground Capacitor Figure 5. Output Driving Two Channels Measurement Point RX ZCH CF RS DRCG Lite RT = ZCH RP CMID CMID RX ZCH RP RT = ZCH RX RS CF RT = ZCH ZCH CMID RX Measurement Point ZCH RT = ZCH Dual Channel Output Driver Figure 5 shows the clock driver driving two high-impedance channels. The purpose of the series resistors RX is to decouple the two channels, and prevent noise from one channel from coupling onto the second channel. With ZCH = 40  and the series resistor set to RX = 16 , the channel becomes an effective 56- channel. The two channels in parallel can be treated as a single 28- channel, and all of the external component values listed in Table 3 can be used. Document Number : 38-07466 Rev. *C Page 7 of 13 [+] Feedback CY2212 Signal Waveforms The device parameters defined according to Figure 6 are as follows. A physical signal that appears at the pins of the device is deemed valid or invalid depending on its voltage and timing relations with other signals. This section defines the voltage and timing waveforms for the input and output pins of the CY2212. The Device Specifications tables list the specifications for the device parameters that are defined here. Table 4. Definition of Device Parameters Parameter VOH, VOL Input and Output voltage waveforms are defined as shown in Figure 6. Both rise and fall times are defined between the 20% and 80% points of the voltage swing, with the swing defined as VH – VL. For example, the output voltage swing VCOS = VOH – VOL. Definition Clock output high and low voltages VCOS Clock output swing VCOS = VOH – VOL VCM Common-mode voltage VCM = (VOH – VOL)/2 VIH, VIL Vdd LVCMOS input high and low voltages tCR, tCF Clock output rise and fall times tCR, CF Clock output rise/fall time delta tCR,CF = tCR – tCF Figure 6. Voltage Waveforms VOH 80% V(t) 20% tCF VOL tCR Figure 7. Crossing Point Voltage CLK CLKB Vx+ Vx,nom Vx– Figure 7 shows the definition of output crossing point. The nominal crossing point between the complementary outputs is defined to be at the 50% point of the DC voltage levels. There are two crossing points defined, Vx+ at the rising edge of CLK and Vx– at the falling edge of CLK. For some clock waveforms, both Vx+ and Vx– might be below Vx, nominal (for example, if tCR is larger than tCF). Vx is defined as the differential output crossing point voltage. Document Number : 38-07466 Rev. *C Page 8 of 13 [+] Feedback CY2212 Figure 8 shows the definition of long-term duty cycle, which is simply the waveform high-time divided by the cycle time (defined at the crossing point). Long-term duty cycle is the average over many (>10,000) cycles. Short-term duty cycle is defined in the next section. DC is defined as the output clock long-term duty cycle. Jitter This section defines the specifications that relate to timing uncertainty (or jitter) of the input and output waveforms. Figure 9 shows the definition of long-term jitter with respect to the falling edge of the CLK signal. Long-term jitter is the difference between the minimum and maximum cycle times. Equal requirements apply for rising edges of the CLK signal. tJL is defined as the output long-term jitter. Figure 8. Duty Cycle CLK CLKB tPW+ tCYCLE DC = tPW + /tCYCLE Figure 9. Long-Term Jitter CLK CLKB tCYCLE tJL = tCYCLE,max – tCYCLE,min over 10000 cycles Figure 10. Cycle-to-Cycle Jitter CLK CLKB tCYCLE,i tCYCLE,i+1 tJ = tCYLCE,i – tCYCLE,i + 1 over 10000 consecutive cycles Document Number : 38-07466 Rev. *C Page 9 of 13 [+] Feedback CY2212 Figure 10 shows the definition of cycle-to-cycle jitter with respect to the falling edge of the CLK signal. Cycle-to-cycle jitter is the difference between cycle times of adjacent cycles. Equal requirements apply for rising edges of the CLK signal. tJ is defined as the clock output cycle-to-cycle jitter. Figure 11 shows the definition of four-cycle short-term jitter. Short-term jitter is defined with respect to the falling edge of the CLK. Four-cycle short-term jitter is the difference between the cumulative cycle times of adjacent four cycles. Equal requirements apply for rising edges of the CLK signal. Equal requirements also apply for two-cycle short-term jitter and three-cycle short-term jitter, and for five-cycle short-term jitter and six-cycle short-term jitter. tJ is defined as the clock output short-term jitter over 2, 3, 4, 5, or 6 cycles. The purpose of this definition of short-term jitter is to define errors in the measured time (for example, t4CYCLE,i) vs. the expected time. The purpose for measuring the adjacent time t4CYCLE, i+1 is only to help determine the expected time for t4CYCLE, i. Alternate methods of determining tJ are possible, including comparing the measured time to an expected time based on a local cycle time, tCYCLE,LOCAL. This local cycle time could be determined by taking the rolling average of a group of cycles (5–10 cycles) preceding the measured cycles. However, it is important to differentiate this rolling average from the average cycle time, tCYCLE,AVG, which is the average cycle time over the 10,000 cycles. Using a long-term average instead of a rolling average would define tJ as a long-term jitter instead of a short-term jitter, and would normally giver overly pessimistic results. Figure 12 shows the definition of cycle-to-cycle duty cycle error. Cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles. Equal requirements apply to the low-times. tDC,ERR is defined as the clock output cycle-to-cycle duty cycle error. Figure 11. Short-Term Jitter CLK CLKB t4CYCLE,i+1 t4CYCLE,i tJ = t4CYCLE,i – t4CYCLE,i+1 over 10000 consecutive cycles Figure 12. Cycle-to-Cycle Duty Cycle Error Cycle i CLK Cycle i+1 CLKB tPW+,i+1 tPW+,i tCYCLE,i+1 tCYCLE,i+1 tDC,ERR = tPW+,i – tPW+,i+1 Figure 13. LCLK Jitter LCLK T 10*T Document Number : 38-07466 Rev. *C Page 10 of 13 [+] Feedback CY2212 Figure 13 shows the definition of LCLK cycle jitter and LCLK 10-cycle jitter. These parameters apply to the LCLK output, and not to the Rambus channel clock outputs. LCLK cycle jitter is the variation in the clock period, T, over a continuous set of clock cycles. The difference bet ween the maximum period and the nominal period in the set of clock cycles measured would be compared to the max spec listed in the AC Device Specifications on page 5. LCLK cycle jitter is measured between rising edges at 50% of the output voltage, and is measured continuously over 30,000 cycles. LCLK 10-cycle jitter is the variation in the time of 10 clock cycles, 10*T, where T is the clock period. The difference between the maximum 10-cycle period and the nominal 10-cycle period in the set of clock cycles measured would be compared to the max spec listed in the AC Device Characteristics Table on page 5. Note that the specification for LCLK 10-cycle jitter is defined based on the measured value of LCLK cycle jitter. LCLK 10-cycle jitter is measured between the first rising edge and the tenth rising edge at 50% of the output voltage, and is measured over 30,000 continuous cycles. tJC,L is defined as the LCLK output cycle jitter, and tJ10,L is defined as the LCLK output jitter over 10 cycles. Measurement The short-term jitter specification (over one to six cycles) for the clock source is given as tJ, as previously shown. Jitter should be measured using a jitter measurement system that has the flexibility of measuring cycle-to-cycle jitter as a function of cycle count. It is important that the short-term jitter be measured over consecutive cycles in order to prevent long-term drift from causing overly pessimistic results. When measured over 10,000 consecutive cycles, the short-term jitter measurements generate large amounts of data which can be viewed in a histogram. Figure 14 shows an example histogram of data from a 4-cycle short-term jitter measurement, with results that are within spec lines for tJ. Note that the jitter is specified as peak-to-peak, so the center of the histogram need not be exactly zero. Further details of jitter measurement methodologies are given in the Rambus DRCG-Lite Specification Appendix A published by Rambus, Inc. Figure 14. Example Jitter Measurement Histogram 4 Cycle Jitter Jitter Spec Ordering Code CY2212ZXC-2 CY2212ZXC-2T Package Type Operating Range 16-Pin TSSOP, Pb-free Commercial 16-Pin TSSOP, Pb-free –Tape and Reel Commercial Document Number : 38-07466 Rev. *C Page 11 of 13 [+] Feedback CY2212 Package Drawing and Dimensions Figure 15. 16-Pin TSSOP 4.40 mm Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Document Number : 38-07466 Rev. *C Page 12 of 13 [+] Feedback CY2212 Document History Page Document Title: CY2212 Direct Rambus Clock Generator (Lite) Document Number: 38-07466 Revision ECN Orig. of Change Submission Description of Change Date ** 117801 CKN 12/10/02 New datasheet *A 308300 RGL See ECN Corrected Ordering Info from -1 to -2 Added Lead Free Devices (-2) Added CXTAL specs in the AC Electrical specifications table *B 2762435 KVM 09/11/09 Remove CY2212ZC-2 and CY2212ZC-2T from Ordering Information table *C 2906466 CXQ 04/07/10 Parts CY2212ZC-2 and CY2212ZC-2T are inactive; obsolete data sheet. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number : 38-07466 Rev. *C Revised April 7, 2010 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback