CY2309NZSXC-1HT

CY2309NZ Nine-Output 3.3V Buffer Features ■ ■ ■ Functional Description The CY2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. The part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133.33 MHz. The CY2309NZ is designed for low EMI and power optimization. It has multiple VSS and VDD pins for noise optimization and consumes less than 32 mA at 66.6 MHz, making it ideal for the low-power requirements of mobile systems. It is available in an ultra-compact 150-mil 16-pin SOIC package. One-input to nine-output buffer/driver Supports two DIMMs or four SO-DIMMs with one additional output for feedback to an external or chipset PLL Low power consumption for mobile applications ❐ Less than 32 mA at 66.6 MHz with unloaded outputs 1-ns Input-Output delay Buffers all frequencies from DC to 133.33 MHz Output-output skew less than 250 ps Multiple VDD and VSS pins for noise and electromagnetic interference (EMI) reduction Space-saving 16-pin 150-mil SOIC package 3.3V operation Industrial temperature available ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram BUF_IN OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 OUTPUT9 Cypress Semiconductor Corporation Document #: 38-07182 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 23, 2008 [+] Feedback CY2309NZ Pinouts Figure 1. CY2309NZ - 16 SOIC-Top View BUF_IN OUTPUT1 OUTPUT2 VDD GND OUTPUT3 OUTPUT4 VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OUTPUT9 OUTPUT8 OUTPUT7 VDD GND OUTPUT6 OUTPUT5 GND Table 1. Pin Description for CY2309NZ Pin 4, 8, 13 5, 9, 12 1 VDD GND BUF_IN Signal 3.3V Digital Voltage Supply Ground Input Clock Outputs Description 2, 3, 6, 7, 10, OUTPUT [1:9] 11, 14, 15, 16 Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except REF) ............ –0.5V to VDD + 0.5V DC Input Voltage REF .........................................–0.5V to 7V Storage Temperature ................................. –65°C to +150°C Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ >2,000V Operating Conditions for Commercial and Industrial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage (Ambient Operating Temperature) Commercial (Ambient Operating Temperature) Industrial Load Capacitance, Fout < 100 MHz Load Capacitance,100 MHz < Fout < 133.33 MHz Input Capacitance DC 0.05 Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) BUF_IN, OUTPUT [1:9] Operating Frequency Description Min 3.0 0 –40 Max 3.6 70 85 30 15 7 133.33 50 Unit V °C °C pF pF pF MHz ms Electrical Characteristics for Commercial and Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage[1] Input HIGH Voltage[1] VIN = 0V VIN = VDD IOL = 8 mA IOH = –8 mA Unloaded outputs at 66.66 MHz 2.4 32 2.0 50.0 100.0 0.4 Input LOW Current Input HIGH Current Output LOW Output HIGH Voltage[2] Voltage[2] Test Conditions Min Max 0.8 Unit V V μA μA V V mA Supply Current Notes 1. BUF_IN input has a threshold voltage of VDD/2. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Document #: 38-07182 Rev. *E Page 2 of 6 [+] Feedback CY2309NZ Switching Characteristics for Commercial and Industrial Temperature Devices[3] Parameter Duty Cycle t3 t4 t5 t6 Rise Time Fall Time [2] Name [2] Description Measured at 1.4V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V [2] Min 40.0 Typ. 50.0 Max 60.0 1.50 1.50 250 Unit % ns ns ps ns = t2 ÷ t1 [2] Output to Output Skew All outputs equally loaded Measured at VDD/2 1 5 Propagation Delay, BUF_IN Rising Edge to OUTPUT Rising Edge[2] 9.2 Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V Figure 3. All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V Figure 4. Output-Output Skew 1.4V OUTPUT OUTPUT t5 1.4V Figure 5. Input-Output Propagation Delay VDD/2 INPUT OUTPUT t6 VDD/2 Note 3. All parameters specified with loaded outputs. Document #: 38-07182 Rev. *E Page 3 of 6 [+] Feedback CY2309NZ Test Circuits VDD 0.1 μF CLK out OUTPUTS C LOAD VDD 0.1 μF GND GND Ordering Information Ordering Code CY2309NZSC–1H[4] CY2309NZSC–1HT[4] Pb-free CY2309NZSXC–1H CY2309NZSXC–1HT CY2309NZSXI-1H CY2309NZSXI-1HT 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel Commercial Commercial Industrial Industrial 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel Package Type Operating Range Commercial Commercial Package Diagram 16 Lead (150 Mil) SOIC 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] Figure 6. 16-Pin (150-Mil) SOIC S16 PIN 1 ID PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B Note 4. Not recommended for new designs. Document #: 38-07182 Rev. *E Page 4 of 6 [+] Feedback CY2309NZ Document History Page Document Title: CY2309NZ Nine-Output 3.3V Buffer Document Number: 38-07182 REV. ** *A *B *C *D ECN 111858 121834 130563 212991 270149 Orig. of Change DSG RBI SDR RGL/GGK RGL Submission Date 12/09/01 12/14/02 10/23/03 03/30/04 10/04/04 Description of Change Change from Spec number: 38-00709 to 38-07182 Power-up requirements added to Operating Conditions Information Added industrial operating temperature to operating conditions Updated the propagation delay T6 spec to 9.2 ns in the Switching Characteristics table Added Lead-free devices Replaced 8.7ns Input/Output Delay to 1ns Input/Output Delayin the features section Updated template. Added Note “Not recommended for new designs.” Changed "SDRAM [1:9]" to "OUTPUT [1:9]" in Operating Conditions table. Removed part number CY2309NZSI–1H and CY2309NZSI–1HT. *E 2568533 AESA 09/23/08 Document #: 38-07182 Rev. *E Page 5 of 6 [+] Feedback CY2309NZ Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. 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Document #: 38-07182 Rev. *E Revised September 23, 2008 Page 6 of 6 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback