CY23EP09SXC-1H

CY23EP09 2.5 V or 3.3 V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer Features ■ ■ ■ Functional Description The CY23EP09 is a 2.5 V or 3.3 V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3 V (2.5 V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The phase-locked loop (PLL) feedback is on-chip and is obtained from the CLKOUT pad. There are two banks of four outputs each, which can be controlled by the Select inputs as shown in the “Select Input Decoding” table on page 4. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The PLL enters a power-down mode when there are no rising edges on the REF input (less than ~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 A of current draw. In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves like a non-zero delay buffer in this mode, and the outputs are not tri-stated. The CY23EP09 is available in different configurations, as shown in the Ordering Information table. The CY23EP09-1 is the base part. The CY23EP09-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5 V input-tolerant applications 10 MHz to 220 MHz maximum operating range Zero input-output propagation delay, adjustable by loading on CLKOUT pin Multiple low-skew outputs — 45 ps typical output-output skew — One input drives nine outputs, grouped as 4 + 4 + 1 ■ ■ ■ ■ 25 ps typical cycle-to-cycle jitter 15 ps typical period jitter Standard and High drive strength options Available in space-saving 16-pin 150-mil small outline integrated circuit (SOIC) or 4.4-mm thin shrunk small outline package (TSSOP) packages 3.3 V or 2.5 V operation Industrial temperature available ■ ■ Block Diagram PLL REF MUX CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 S2 Select Input Decoding S1 CLKB1 CLKB2 CLKB3 CLKB4 Cypress Semiconductor Corporation Document #: 38-07760 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 1, 2011 [+] Feedback CY23EP09 Contents Pin Configuration ............................................................. 3 Pin Definition .................................................................... 4 Select Input Decoding ...................................................... 4 Zero Delay and Skew Control .......................................... 4 Absolute Maximum Conditions ....................................... 5 Operating Conditions ....................................................... 5 3.3 V DC Electrical Specifications ................................... 5 2.5 V DC Electrical Specifications ................................... 6 3.3 V and 2.5 V AC Electrical Specifications .................. 6 Switching Waveforms ...................................................... 8 Test Circuits ...................................................................... 8 Supplemental Parametric Information ............................ 9 Ordering Code Definition ........................................... 13 Package Drawing and Dimensions ............................... 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 Document #: 38-07760 Rev. *C Page 2 of 17 [+] Feedback CY23EP09 Pin Configuration Top View REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Document #: 38-07760 Rev. *C Page 3 of 17 [+] Feedback CY23EP09 Pin Definition Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[1] CLKA1[2] CLKA2[2] VDD GND CLKB1[2] CLKB2[2] S2 [3] Signal Input reference frequency Buffered clock output, Bank A Buffered clock output, Bank A 3.3 V or 2.5 V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground 3.3 V or 2.5 V supply Buffered clock output, Bank A Buffered clock output, Bank A Description S1[3] CLKB3[2] CLKB4[2] GND VDD CLKA3[2] CLKA4[2] CLKOUT[2] Buffered output, internal feedback on this pin Select Input Decoding S2 0 0 1 1 S1 0 1 0 1 CLOCK A1–A4 Three-state Driven Driven Driven CLOCK B1–B4 Three-state Three-state Driven Driven CLKOUT[4] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. The output driving the CLKOUT pin will be driving a total load of 5 pF plus any additional load externally connected to this pin. For applications requiring zero input-output delay, the total load on each output pin (including CLKOUT) must be the same. If input-output delay adjustments are required, the CLKOUT load may be changed to vary the delay between the REF input and remaining outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”. Notes 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document #: 38-07760 Rev. *C Page 4 of 17 [+] Feedback CY23EP09 Absolute Maximum Conditions Supply voltage to ground potential .................–0.5 V to 4.6 V DC input voltage .....................................VSS – 0.5 V to 4.6 V Storage temperature................................... –65 °C to 150 °C Junction temperature.................................................. 150 °C Static discharge voltage (per MIL-STD-883, Method 3015............................. > 2000 V Min 3.0 2.3 0 –40 – – – – – – – – 1–1.5 0.8 29 41 37 41 0.01 95 70 58 48 50 Max 3.6 2.7 70 85 30 30 22 22 15 15 15 5 Unit V V °C °C pF pF pF pF pF pF pF pF MHz MHz     ms °C/W °C/W °C/W °C/W Operating Conditions Parameter VDD3.3 VDD2.5 TA CL[5] 3.3 V supply voltage 2.5 V supply voltage Operating temperature (ambient temperature)—commercial Operating temperature (ambient temperature)—industrial Load capacitance,