CY23S09SXC-1T

CY23S09, CY23S05 Low Cost 3.3 V Spread Aware Zero Delay Buffer Features ■ 10 MHz to 100 MHz and 133 MHz operating range, compatible with CPU and PCI bus frequencies ■ Zero input-output propagation delay ■ Multiple low skew outputs ❐ Output-output skew less than 250 ps ❐ Device-device skew less than 700 ps ❐ One input drives five outputs (CY23S05) ❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY23S09) ■ Less than 200 ps Cycle-to-cycle jitter ■ Test mode to bypass PLL (CY23S09 only, see Select Input Decoding for CY23S09 on page 4) ■ Available in space saving 16-pin, 150-mil SOIC, 4.4 mm TSSOP (CY23S09) or 8-pin, 150-mil SOIC package (CY23S05) ■ 3.3 V operation, advanced 0.65 CMOS technology ■ Spread Aware Functional Description The CY23S09 is a low cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC package. The CY23S05 is an 8-pin version of the CY23S09. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100 and 133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23S09 has two bans of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding table on Select Input Decoding for CY23S09 on page 4. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY23S09 and CY23S05 PLLs enter a power down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 A of current draw (for commercial temperature devices) and 25.0 A (for industrial temperature devices). The CY23S09 PLL shuts down in one additional case, as shown in the Select Input Decoding for CY23S09 on page 4. Multiple CY23S09 and CY23S05 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps; the output to output skew is guaranteed to be less than 250 ps. The CY23S05 and CY23S09 is available in two different configurations, as shown in the Ordering Information on page 8. The CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H and CY23S09-1H is the high drive version of the -1, and its rise and fall times are much faster than -1. For a complete list of related resources, click here. Logic Block Diagram Cypress Semiconductor Corporation Document Number: 38-07296 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 07, 2014 CY23S09, CY23S05 Contents Pinouts .............................................................................. 3 Select Input Decoding for CY23S09 ................................ 4 Functional Overview ........................................................ 4 Zero Delay and Skew Control ..................................... 4 Spread Aware.............................................................. 4 Maximum Ratings ............................................................. 5 Operating Conditions for CY23S05SXX-XX and CY23S09SXX-XX (Industrial, Commercial Devices) ............. 5 Electrical Characteristics for CY23S05SXX-XX and CY23S09SXX-XX (Industrial, Commercial Devices) .......... 5 Switching Characteristics for CY23S05SXC-1 and CY23S09SXC-1 Commercial Temperature Devices............... 5 Switching Characteristics for CY23S05SXI-1H Industrial Temperature Devices.......................................................................... 6 Switching Waveforms ...................................................... 6 Test Circuits ...................................................................... 7 Document Number: 38-07296 Rev. *I Thermal Resistance .......................................................... 7 Ordering Information ........................................................ 8 Ordering Code Definitions ........................................... 8 Package Diagrams ............................................................ 9 Acronym .......................................................................... 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support....................... 13 Products .................................................................... 13 PSoC® Solutions ...................................................... 13 Cypress Developer Community................................. 13 Technical Support ..................................................... 13 Page 2 of 13 CY23S09, CY23S05 Pinouts Figure 1. Pin Configuration – CY23S09 Figure 2. Pin Configuration – CY23S05 Table 1. Pin Description for CY23S09 Pin Signal Description 1 REF[1] Input reference frequency, 5 V tolerant input 2 CLKA1[2] Buffered clock output, bank A 3 CLKA2[2] Buffered clock output, bank A 4 VDD 3.3 V supply 5 GND Ground 6 CLKB1[2] Buffered clock output, bank B 7 CLKB2[2] Buffered clock output, bank B 8 S2[3] Select input, bit 2 9 S1[3] Select input, bit 1 10 CLKB3[2] Buffered clock output, bank B 11 CLKB4[2] Buffered clock output, bank B 12 GND Ground 13 VDD 3.3 V supply 14 CLKA3[2] Buffered clock output, bank A 15 CLKA4[2] Buffered clock output, bank A 16 CLKOUT[2] Buffered output, internal feedback on this pin Table 2. Pin Description for CY23S05 Pin Signal Description 1 REF[1] Input reference frequency, 5 V tolerant input 2 CLK2[2] Buffered clock output 3 CLK1[2] Buffered clock output 4 GND Ground 5 CLK3[2] Buffered clock output 6 VDD 3.3 V supply 7 CLK4[2] Buffered clock output 8 CLKOUT[2] Buffered clock output, internal feedback on this pin Notes 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull up on these inputs. Document Number: 38-07296 Rev. *I Page 3 of 13 CY23S09, CY23S05 Select Input Decoding for CY23S09 S2 0 0 1 1 S1 0 1 0 1 CLOCK A1–A4 Three-state Driven Driven Driven CLOCK B1–B4 Three-state Three-state Driven Driven Functional Overview Zero Delay and Skew Control All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Because the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, to obtain zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. CLKOUT[4] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N Spread Aware Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. Cypress is one of the pioneers of SSFTG development and designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress Whitepaper EMI and Spread Spectrum Technology. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note titled AN1234 - Understanding Cypress’s Zero Delay Buffers. Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins Note 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document Number: 38-07296 Rev. *I Page 4 of 13 CY23S09, CY23S05 Maximum Ratings Supply voltage to ground potential ...............–0.5 V to +7.0 V Maximum soldering temperature (10 seconds) ......... 260 C DC input voltage (Except REF) .......... –0.5 V to VDD + 0.5 V Junction temperature................................................. 150 C DC input voltage REF  0.5 V to 7 V Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2,000 V Storage temperature ................................ –65 C to +150 C Operating Conditions for CY23S05SXX-XX and CY23S09SXX-XX (Industrial, Commercial Devices)[5] Parameter VDD TA Description Supply voltage Operating temperature - Ambient (Commercial) Operating temperature - Ambient (Industrial) Min Max Unit 3.0 3.6 V 0 70 C -40 85 C CL Load capacitance, below 100 MHz 30 pF CL Load capacitance, from 100 MHz to 133 MHz 10 pF CIN Input capacitance 7 pF Electrical Characteristics for CY23S05SXX-XX and CY23S09SXX-XX (Industrial, Commercial Devices) Parameter Description Test Conditions Min Max voltage[6] Unit VIL Input LOW VIH Input HIGH voltage[6] IIL Input LOW current VIN = 0 V 50.0 A IIH Input HIGH current VIN = VDD 100.0 A VOL Output LOW voltage[7] IOL = 8 mA (–1) IOH = 12 mA (–1H) 0.4 V VOH Output HIGH voltage[7] IOH = –8 mA (–1) IOL = –12 mA (–1H) 0.8 V 2.0 V 2.4 V IDD (PD mode) Power-down supply current REF = 0 MHz 12.0 A IDD 32.0 mA Supply current Unloaded outputs at 66.67 MHz, SEL inputs at VDD Switching Characteristics for CY23S05SXC-1 and CY23S09SXC-1 Commercial Temperature Devices [8] Parameter t1 Description Output frequency Test Conditions 30 pF load 10 pF load Duty cycle[7] = t2  t1 t7 tJ Measured at 1.4 V, Fout = 66.67 MHz Rise time Measured between 0.8 V and 2.0 V Fall time[7] Measured between 0.8 V and 2.0 V Output-to-output skew[7] All outputs equally loaded Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[7] Device-to-device skew[7] Measured at VDD/2 on the CLKOUT pins Cycle-to-cycle jitter[7] Measured at 66.67 MHz, loaded outputs tLOCK PLL lock time[7] t3 t4 t5 t6 Min 10 10 Typ Max 100 133.33 Unit MHz MHz 40.0 50.0 60.0 2.50 2.50 250 ±350 % ns ns ps ps 700 200 ps ps 1.0 ms [7] Stable power supply, valid clock presented on REF pin 0 0 Notes 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 6. REF input has a threshold voltage of VDD/2. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters specified with loaded outputs. Document Number: 38-07296 Rev. *I Page 5 of 13 CY23S09, CY23S05 Switching Characteristics for CY23S05SXI-1H Industrial Temperature Devices[8] Parameter t1 Description Test Conditions Min Typ Unit 100 133.33 MHz MHz Output frequency 30 pF load 10 pF load Duty cycle[7] = t2  t1 Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 % Duty cycle[7] = t2  t1 Measured at 1.4 V, Fout