CY23FP12OXC-002T

CY23FP12-002 200-MHz Field Programmable Zero Delay Buffer Features ■ ■ Functional Description The CY23FP12-002 is a pre-programmed version of the CY23FP12. It features a high-performance fully field-programmable 200-MHz zero delay buffer designed for high-speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high-performance ASICs and microprocessors. The CY23FP12-002 is fully programmable through volume or prototype programmers, enabling the user to define an application-specific zero delay buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths. For additional flexibility, the user can mix and match multiple functions, listed in Table 2 on page 5, and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature enables the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12-002 also features a proprietary auto power down circuit that shuts down the device in case of a REF failure, resulting in less than 50 μA of current draw. The CY23FP12-002 provides 12 outputs grouped in two banks with separate power supply pins which can be connected independently to either a 2.5 V or a 3.3 V rail. Selectable reference input is a fault tolerance feature which allows for glitch-free switch over to secondary clock source when REFSEL is asserted/deasserted. Pre-programmed configuration Fully field-programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop (PLL) or fanout buffer configuration 10 MHz to 200 MHz operating range Split 2.5-V or 3.3-V outputs Two low-voltage complementary metal oxide semiconductor (LVCMOS) reference inputs Twelve low-skew outputs ❐ Output-output skew < 200 ps ❐ Device-device skew < 500 ps Input-output skew < 250 ps Cycle-cycle jitter < 100 ps (typical) Three-stateable outputs Less than 50 μA shutdown current Spread Aware™ 28-pin shrunk small outline package (SSOP) 3.3-V operation ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram VDDC VDDA CLKA0 Lock Detect CLKA1 CLKA2 CLKA3 REFSEL REF1 REF2 FBK ÷M ÷N 100 to 400MHz PLL ÷1 ÷2 ÷3 ÷4 ÷X ÷2X CLKA4 CLKA5 VSSA VDDB CLKB0 CLKB1 CLKB2 CLKB3 Test Logic S[2:1] VSSC F unction Selection CLKB4 CLKB5 VSSB Cypress Semiconductor Corporation Document #: 38-07644 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 18, 2011 [+] Feedback CY23FP12-002 Contents Pin Configuration ............................................................. 3 Pin Description ................................................................. 3 Field Programming the CY23FP12-002 ...................... 7 CyberClocks™ Software .............................................. 7 CY3672-USB Development Kit ................................... 7 CY23FP12-002 Frequency Calculation ........................... 7 Absolute Maximum Conditions....................................... 8 Operating Conditions....................................................... 8 DC Electrical Specifications ............................................ 8 Switching Characteristics [5] .......................................... 9 Switching Waveforms .................................................... 10 Ordering Information...................................................... Ordering Code Definition........................................... Package Drawing and Dimension ................................. Acronyms ....................................... Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 11 11 12 13 13 13 14 14 14 14 14 Document #: 38-07644 Rev. *B Page 2 of 14 [+] Feedback CY23FP12-002 Pin Configuration Figure 1. 28-Pin SSOP REF2 REF1 CLKB0 CLKB1 VSSB CLKB2 CLKB3 VDDB VSSB CLKB4 CLKB5 VDDB VDDC S2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 REFSEL FBK CLKA0 CLKA1 VSSA CLKA2 CLKA3 VDDA VSSA CLKA4 CLKA5 VDDA VSSC S1 Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name REF2 REF1 CLKB0 CLKB1 VSSB CLKB2 CLKB3 VDDB VSSB CLKB4 CLKB5 VDDB VDDC S2 S1 VSSC VDDA CLKA5 CLKA4 VSSA VDDA CLKA3 CLKA2 VSSA CLKA1 CLKA0 FBK REFSEL I I O O PWR O O PWR PWR O O PWR PWR I I PWR PWR O O PWR PWR O O PWR O O I I I/O Type LVTTL/LVCMOS LVTTL/LVCMOS LVTTL LVTTL POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER LVTTL LVTTL LVTTL LVTTL Description Input reference frequency, 5V-tolerant input. Input reference frequency, 5V-tolerant input. Clock output, Bank B. Clock output, Bank B. Ground for Bank B. Clock output, Bank B. Clock output, Bank B. 2.5-V or 3.3-V supply, Bank B. Ground for Bank B. Clock output, Bank B. Clock output, Bank B. 2.5-V or 3.3-V supply, Bank B. 3.3 V core supply. Select input. Select input. Ground for core. 2.5-V or 3.3-V supply, Bank A. Clock output, Bank A. Clock output, Bank A. Ground for Bank A. 2.5-V or 3.3-V supply Bank A. Clock output, Bank A. Clock output, Bank A. Ground for Bank A. Clock output, Bank A. CLock output, Bank A. PLL feedback input. Reference select input. When REFSEL = 0, REF1 is selected. When REFSEL = 1, REF2 is selected. Document #: 38-07644 Rev. *B Page 3 of 14 [+] Feedback CY23FP12-002 Figure 2. Basic PLL Block Diagram /1,/2,/3,/4, /x,/2x CLKB5 CLKB4 /1,/2,/3,/4, /x,/2x CLKB3 CLKB2 REF /M PLL /1,/2,/3,/4, /x,/2x Output Function Select Matrix CLKB1 CLKB0 FBK /N /1,/2,/3,/4, /x,/2x CLKA5 CLKA4 /1,/2,/3,/4, /x,/2x CLKA3 CLKA2 /1,/2,/3,/4, /x,/2x CLKA1 CLKA0 Following is a list of independent functions that can be programmed with a volume or prototype programmer on the “pre-programmed” silicon. Table 1. Programmable Functions Configuration DC Drive Bank A Description Default Programs the drive strength of Bank A outputs. The user can select one out +20 mA of two possible drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA. Programs the drive strength of Bank B outputs. The user can select one out +20 mA of two possible drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA. Enables/disables CLKB[5:0] outputs. Each of the six outputs can be disabled Enable individually if not used, to minimize electromagnetic interference (EMI) and switching noise. Enables/disables CLKA[5:0] outputs. Each of the six outputs can be disabled Enable individually if not used, to minimize EMI and switching noise. Generates an inverted clock on the CLKA0 output. When this option is programmed, CLKA0 and CLKA1 will become complimentary pairs. Generates an inverted clock on the CLKA2 output. When this option is programmed, CLKA2 and CLKA3 will become complimentary pairs. Generates an inverted clock on the CLKA4 output. When this option is programmed, CLKA4 and CLKA5 will become complimentary pairs. Generates an inverted clock on the CLKB0 output. When this option is programmed, CLKB0 and CLKB1 will become complimentary pairs. Non invert Non invert Non invert Non invert DC Drive Bank B Output Enable for Bank B clocks Output Enable for Bank A clocks Inv CLKA0 Inv CLKA2 Inv CLKA4 Inv CLKB0 Document #: 38-07644 Rev. *B Page 4 of 14 [+] Feedback CY23FP12-002 Table 1. Programmable Functions (continued) Configuration Inv CLKB2 Inv CLKB4 Pull down Enable Fbk Pull down Enable Fbk Sel Description Generates an inverted clock on the CLKB2 output. When this option is programmed, CLKB2 and CLKB3 will become complimentary pairs. Generates an inverted clock on the CLKB4 output. When this option is programmed, CLKB4 and CLKB5 will become complimentary pairs. Enables/disables internal pulldowns on all outputs Default Non-invert Non-invert Enable Enables/disables internal pulldowns on the feedback path (applicable to both Enable internal and external feedback topologies) Selects between the internal and the external feedback topologies Internal The following table lists independent functions, which can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2 combination is selected, the device assumes the configuration (which is essentially a set of functions given in Table 2) that has been preassigned to that particular combination. Table 2. Programmable Functions for S1/S2 Combinations Function Description Default Enable Enable Enable Enable Enable Enable Output Enable CLKB[5:4] Enables/disables CLKB[5:4] output pair Output Enable CLKB[3:2] Enables/disables CLKB[3:2] output pair Output Enable CLKB[1:0] Enables/disables CLKB[1:0] output pair Output Enable CLKA[5:4] Enables/disables CLKA[5:4] output pair Output Enable CLKA[3:2] Enables/disables CLKA[3:2] output pair Output Enable CLKA[1:0] Enables/disables CLKA[1:0] output pair Auto Power down Enable Enables/disables the auto power down circuit, which monitors the reference clock rising Enable edges and shuts down the device in case of a reference ‘failure.’ This failure is triggered by a drift in reference frequency below a set limit. This auto power down circuit is disabled internally when one or more of the outputs are configured to be driven directly from the reference clock. PLL Power down M[7:0] N[7:0] X[6:0] Shuts down the PLL when the device is configured as a non-PLL fanout buffer. See Table 4 on page 6 Assigns an eight-bit value to reference divider –M. The divider can be any integer value See Table 4 from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. on page 6 Assigns an eight-bit value to feedback divider –N. The divider can be any integer value See Table 4 from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. on page 6 Assigns a seven-bit value to output divider –X. The divider can be any integer value from 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated by the appropriate output mux setting. Selects between the PLL output and the reference clock as the source clock for the output dividers. See Table 4 on page 6 See Table 4 on page 6 Divider Source CLKA54 Source CLKA32 Source CLKA10 Source CLKB54 Source CLKB32 Source CLKB10 Source Independently selects one out of the eight possible output dividers that will connect to See Table 4 the CLKA5 and CLKA4 pair. Please refer to Table 3 on page 6 for a list of divider values. on page 6 Independently selects one out of the eight possible output dividers that will connect to See Table 4 the CLKA3 and CLKA2 pair. Please refer to Table 3 on page 6 for a list of divider values. on page 6 Independently selects one out of the eight possible output dividers that will connect to See Table 4 the CLKA1 and CLKA0 pair. Please refer to Table 3 on page 6 for a list of divider values. on page 6 Independently selects one out of the eight possible output dividers that will connect to See Table 4 the CLKB5 and CLKB4 pair. Please refer to Table 3 on page 6 for a list of divider values. on page 6 Independently selects one out of the eight possible output dividers that will connect to See Table 4 the CLKB3 and CLKB2 pair. Please refer to Table 3 on page 6 for a list of divider values. on page 6 Independently selects one out of the eight possible output dividers that will connect to See Table 4 the CLKB1 and CLKB0 pair. Please refer to Table 3 on page 6 for a list of divider values. on page 6 Document #: 38-07644 Rev. *B Page 5 of 14 [+] Feedback CY23FP12-002 Table 3 is a list of output dividers that are independently selected to connect to each output pair. In the default (pre-programmed) state of the device, S1 and S2 pins will function as indicated in Table 4. The CY23FP12-002 can be programmed to other configurations. Table 3. Output Dividers CLKA/B Source 0 [000] 1 [001] 2 [010] 3 [011] 4 [100] 5 [101] 6 [110] 7 [111] Output Connects To REF Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by X Divide by 2X[1] TEST mode [LOCK signal][2] Table 4. Pre-Programmed Configuration Outputs ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 S2, S1 00 00 00 00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11 11 11 11 DivSrc 1 3 X=6 X=6 4 Ref 4 4 4 4 X=8 X=8 X=8 X=8 X=8 4 4 4 Ref Ref Ref 2 2 2 Example Output REF Input (MHz) VCO (MHz) Output (MHz) 25 200 200 25 200 66.7 25 200 33.3 25 200 33.3 25 200 50 25 200 25 100 200 50 100 200 50 100 200 50 100 200 50 100 200 25 100 200 25 33.3 266.6 33.3 33.3 266.6 33.3 33.3 266.6 33.3 33.3 266.6 66.6 33.3 266.6 66.6 33.3 266.6 66.6 100 powerdown 100 100 powerdown 100 100 powerdown 100 100 powerdown 50 100 powerdown 50 100 powerdown 50 Notes 1. Outputs will be rising edge aligned only to those outputs using this same device setting. 2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode. Document #: 38-07644 Rev. *B Page 6 of 14 [+] Feedback CY23FP12-002 Field Programming the CY23FP12-002 The CY23FP12-002 comes pre-programmed and ready for use, but it can also be reprogrammed to any other valid configuration. When programming, it must be programmed in a device programmer prior to being installed in a circuit. The CY23FP12-002 is based on flash technology, so it can be reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities can be programmed on the CY3672-USB programmer. Cypress’s value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others are available for large production quantities. CY23FP12-002 Frequency Calculation The CY23FP12-002 is an extremely flexible clock buffer with up to 12 individual outputs, generated from an integrated PLL. Four variables are used to determine the final output frequency. These are the input reference frequency, the M and N dividers, and the post divider. The basic PLL block diagram is shown in Figure 2 on page 4. Each of the six clock output pairs has many post divider options available to it. X is a programmable value between 5 and 130, and 2X is twice that value. There are six post divider options: /1, /2, /3, /4, /X, and /2X. The post divider options can be applied to the calculated PLL frequency or to the REF directly. The feedback is connected either internally to CLKA0 or externally to any output. A programmable divider, M, is inserted between the reference input, REF, and the phase detector. The divider M can be any integer 1 to 256. The PLL input frequency cannot be lower than 10 MHz or higher than 200 MHz. A programmable divider, N, is inserted between the feedback input, FBK, and the phase detector. The divider N can be any integer 1 to 256. The PLL input frequency cannot be lower than 10 MHz or higher than 200 MHz. The output can be calculated as follows: FREF / M = FFBK / N. FPLL = (FREF * N * post divider) / M. FOUT = FPLL / post divider. In addition to above divider options, another option bypasses the PLL and passes the REF directly to the output. FOUT = FREF. CyberClocks™ Software CyberClocks is an easy-to-use software application that allows the user to custom-configure the CY23FP12-002. Users can specify the REF, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyberClocks outputs an industry standard JEDEC file used for programming the CY23FP12-002. CyberClocks can be downloaded free of charge from the Cypress website at www.cypress.com. CY3672-USB Development Kit The Cypress CY3672-USB Developer Kit, in combination with the CY3692 Socket Adapter, is used to program samples and small prototype quantities of the CY23FP12-002. This portable programmer connects to a PC through a USB interface. The JEDEC file output of CyberClocks can be downloaded to the portable programmer for small-volume programming, or for use with a production programming system for larger volumes. Document #: 38-07644 Rev. *B Page 7 of 14 [+] Feedback CY23FP12-002 Absolute Maximum Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Parameter VDD VIN VIN LUI TS TJ ØJc ØJa ESDh MSL GATES UL–94 FIT Description Supply voltage Input voltage REF Input voltage Except REF Latch up immunity Temperature, storage Junction temperature Dissipation, junction to case Dissipation, junction to ambient ESD protection (human body model) Moisture sensitivity level Total functional gate count Flammability rating Failure in time Condition Nonfunctional Relative to VCC Relative to VCC Functional Nonfunctional Functional Functional Min. –0.5 –0.5 –0.5 300 –65 – 34 86 2000 MSL – 1 21375 V–0 10 125 125 Max. 7 VDD + 0.5 VDD + 0.5 Unit VDC VDC VDC mA °C °C °C/W °C/W V class each class ppm Assembled die At 1/8 in. Manufacturing test Operating Conditions Parameter VDDC VDDA, VDDB TA tPU Description Core supply voltage Bank A, bank B supply voltage Test Conditions Min. 3.135 3.135 2.375 0 0.05 Max. 3.465 3.465 2.625 70 500 Unit V V V °C ms Temperature, operating ambient Commercial temperature Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) DC Electrical Specifications Parameter VIL VIH IIL IIH VOL VOH IDDS IDD Description Test Conditions Min. Typ. Max. Unit Input LOW voltage[3] – – 0.3 × VDD V Input HIGH voltage[3] 0.7 × VDD – – V Input LOW current[3] VIN = 0 V – – 50 μA Input HIGH current[3] VIN = VDD – – 50 μA – – 0.5 V Output LOW voltage[4] VDDA/VDDB = 3.3 V, IOL = 16 mA (standard drive) VDDA/VDDB = 3.3 V, IOL = 20 mA (high drive) VDDA/VDDB = 2.5 V, IOL = 16 mA (high drive) Output HIGH VDDA/VDDB = 3.3 V, IOH = –16 mA (standard drive) VDD – 0.5 – – V voltage[4] VDDA/VDDB = 3.3 V, IOH = –20 mA (high drive) VDDA/VDDB = 2.5 V, IOH = –16 mA (high drive) Power-down supply REF = 0 MHz – 12 50 μA current Supply current VDDA = VDDB = 2.5 V, Unloaded outputs at 166 MHz – 40 65 mA VDDA = VDDB = 2.5 V, Loaded outputs at166 MHz, – 65 100 CL = 15 pF VDDA = VDDB = 3.3 V, Unloaded outputs at 166 MHz – 50 80 – 100 120 VDDA = VDDB = 3.3 V, Loaded outputs at 166 MHz, CL = 15 pF Notes 3. Applies to both REF Clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07644 Rev. *B Page 8 of 14 [+] Feedback CY23FP12-002 Switching Characteristics [5] Parameter fREF ERREF DCREF fOUT DCOUT t3 Description Reference frequency[6] Reference edge rate Reference duty cycle Output frequency [7] Test Conditions Min 10 1 25 Typ – – – – – 50 50 – – – – – – – – – Max 200 – 75 200 100 55 60 1.6 0.8 2.0 1.0 1.6 0.8 1.6 0.8 650 Unit MHz V/ns % MHz % ns CL = 15 pF CL = 30 pF VDDA/B = 3.3 V, measured at VDD/2 VDDA/B = 2.5 V, measured at VDD/2 VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 30 pF (standard drive and high drive) VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 15 pF (standard drive and high drive) VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 30 pF (high drive only) VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 15 pF (high drive only) 10 10 45 40 – – – – – – – – – Output duty cycle[5] Rise time[5] t4 Fall time[5] VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 30 pF (standard drive and high drive) VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 15 pF (standard drive and high drive) VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 30 pF (high drive only) VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 15 pF (high drive only) ns TTB Total timing budget,[8,9] Bank A and B same frequency Total timing budget, bank A and B different frequency Outputs at 200 MHz, tracking skew not included ps – All outputs equally loaded Same frequency Different frequency Different voltage, same frequency – – – – – – – – – – – – – 0 0 – – 850 200 200 400 400 250 500 200 400 ps ps ps ps t5 Output-to-output skew[5] Bank-to-bank skew Bank-to-bank skew Bank-to-bank skew t6 t7 tJ Input-to-output skew (static Measured at VDD/2, REF to FBK phase offset)[5] Device-to-device skew[5] Cycle-to-cycle (Peak-to-peak) jitter[5] Measured at VDD/2 Bank A and B same frequency Bank A and B different frequency Cycle-to-cycle jitter[[5] (Peak-to-peak) Notes 5. All parameters are specified with loaded outputs. 6. When the device is configured as a non-PLL fanout buffer (PLL Power down enabled), the reference frequency can be lower than 10MHz. With auto power down disabled and PLL power down enabled, the reference frequency can be as low as DC level. 7. When the device is configured as a non-PLL fanout buffer (PLL Power down enabled), the output frequency can be lower than 10MHz. With auto power down disabled and PLL power down enabled, the output frequency can be as low as DC level. 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency. Document #: 38-07644 Rev. *B Page 9 of 14 [+] Feedback CY23FP12-002 Switching Characteristics (continued)[5] Parameter tTSK tLOCK tLD Description Tracking skew PLL lock time[5] Inserted loop delay Test Conditions Input reference clock at < 50-KHz modulation with ±3.75% spread Stable power supply, valid clock at REF Max loop delay for PLL Lock (stable frequency) Max loop delay to meet Tracking Skew Spec Min – – – – Typ – – – – Max 200 1.0 7 4 Unit ps ms ns ns Switching Waveforms Figure 3. Duty Cycle Timing Figure 4. All Outputs Rise/Fall Time Figure 5. Output-Output Skew Figure 6. Input-Output Propagation Delay Document #: 38-07644 Rev. *B Page 10 of 14 [+] Feedback CY23FP12-002 Figure 7. Device-Device Skew Test Circuits Ordering Information Ordering Code Pb-free CY23FP12OXC-002 CY23FP12OXC-002T Programmer CY3672-USB CY3692 Package Type 28-pin SSOP 28-pin SSOP – Tape and Reel Operating Range Commercial, 0 °C to 70 °C Commercial,0 °C to 70 °C Programmer with USB Interface CY23FP12 Socket Adapter for CY3672-USB Programmer (Label CY3672 ADP006) Ordering Code Definition CY23FP12 OX X (T) Package type: T = tape and reel, blank = tube Temperature code: C = Commercial, I = Industrial Package: 28-pin SSOP, Pb-free Device number Document #: 38-07644 Rev. *B Page 11 of 14 [+] Feedback CY23FP12-002 Package Drawing and Dimension Figure 8. 28-Pin (5.3 mm) Shrunk Small Outline Package 51-85079 *D Document #: 38-07644 Rev. *B Page 12 of 14 [+] Feedback CY23FP12-002 Acronyms Acronym DCXO ESD PLL RMS SSOP XTAL Description digitally controlled crystal oscillator electrostatic discharge phase locked loop root mean square shrunk small outline package crystal Document Conventions Units of Measure Symbol Unit of Measure degree Celsius micro amperes milli amperes milli seconds Mega Hertz nano seconds pico Farad pico seconds Volts °C µA mA ms MHz ns pF ps V Document #: 38-07644 Rev. *B Page 13 of 14 [+] Feedback CY23FP12-002 Document History Page Document Title: CY23FP12-002 200-MHz Field Programmable Zero Delay Buffer Document Number: 38-07644 REV. ** *A ECN NO. 206761 2865396 Submission Date See ECN 01/25/2010 Orig. of Change RGL KVM New Data Sheet Updated template. Removed references to industrial temperature range Added captions to tables 1-4. Added Operating Conditions table. Various edits to text. Removed “FTG” from text about the CY3672 programmer. Added part numbers CY23FP12OXC-002, CY23FP12OXC-002T Removed part numbers CY23FP12OC-002, CY23FP12OC-002T, CY23FP12OI-002 and CY23FP12OI-002T Changed part number CY3672 to CY3672-USB. Updated package drawing. Modified VIN max value from 7 to VDD + 0.5 in Absolute Maximum Conditions. Added Acronyms, Document Conventions, and Ordering Code Definition Description of Change *B 3146346 01/18/2011 BASH Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07644 Rev. *B Revised January 18, 2011 2 Page 14 of 14 CyberClocks™ is a trademark and CyClocks is a registered trademark of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback