CY25403SXIT

CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Features ■ ■ Three fully integrated phase-locked loops (PLLs) Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock Reference clock input voltage range ❐ 1.8 V for CY25403/CY25423/CY25483 Wide operating output frequency range ❐ 3 to 166 MHz Programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483 Selectable output clock voltages independent of VDD supply: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483 Frequency select feature with option to select four different frequencies Power-down, output enable, and SS ON/OFF controls Low jitter, high accuracy outputs Ability to synthesize nonstandard frequencies with Fractional-N capability ■ ■ ■ ■ Three clock outputs with programmable drive strength Glitch-free outputs while frequency switching 8-pin SOIC package Commercial and Industrial temperature ranges ■ Benefits ■ ■ ■ Multiple high performance PLLs allow synthesis of unrelated frequencies Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies Application specific programmable EMI reduction using Spread Spectrum for clocks Programmable PLLs for system frequency margin tests Meets critical timing requirements in complex system designs Suitability for PC, consumer, portable, and networking applications Capable of Zero PPM frequency synthesis error Uninterrupted system operation during clock frequency switch Application compatibility in standard and low power systems ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Block Diagram XIN/ EXCLKIN XOUT OSC PLL1 Crossbar Switch Output Dividers and CLK1 (SS) MUX and FS0 FS1 Control Logic PLL3 (SS) SSON PD#/OE PLL 2 (SS) Drive Strength Control CLK2 (No SS) CLK3 (SS) Cypress Semiconductor Corporation Document #: 001-12564 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 18, 2011 CY25403/CY25423/CY25483 Contents General Description ......................................................... 4 Configurable PLLs ....................................................... 4 Input Reference Clocks ............................................... 4 VDD Power Supply Options ........................................ 4 Spread Spectrum Control ............................................ 4 Frequency Select ........................................................ 4 Glitch-Free Frequency Switch ..................................... 4 PD#/OE Mode ............................................................. 4 Output Drive Strength .................................................. 4 Generic Configuration and Custom Frequency ........... 4 Absolute Maximum Conditions ....................................... 5 DC Electrical Specifications ............................................ 6 AC Electrical Specifications ............................................ 7 Recommended Crystal Specification for SMD Package .............................................................. 7 Recommended Crystal Specification for Thru-Hole Package ..................................................... 8 Test and Measurement Setup .......................................... 8 Voltage and Timing Definitions ....................................... 8 Ordering Information ........................................................ 9 Possible Configurations ............................................... 9 Ordering Code Definitions ......................................... 10 Package Drawing and Dimensions ............................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document #: 001-12564 Rev. *F Page 2 of 14 CY25403/CY25423/CY25483 Table 1. Device Selector Guide Device CY25403/CY25423/CY25483 Yes Crystal Input EXCKLKIN Input 1.8 V LVCMOS VDD 2.5 V, 3.0 V, 3.3 V Figure 1. Pin Diagram - CY25403/CY25423/CY25483 8-Pin SOIC XIN/ EXCLKIN VDD CLK1 CLK2/FS0 1 2 3 4 CY25403 8 7 6 5 XOUT GND CLK3/SSON PD#/OE/FS1 Table 2. Pin Definition - CY25403/CY25423/CY25483 (2.5 V, 3.0 V, or 3.3 V Supply) Pin Number 1 2 3 4 5 6 7 8 VDD CLK1 CLK2/FS0 PD#/OE/FS1 CLK3/SSON GND XOUT Name XIN/EXCLKIN Input Power Output Output/Input Input Output/Input Power Output IO Power supply: 2.5 V, 3.0 V, or 3.3 V Programmable clock output with spread spectrum Multifunction programmable pin: programmable clock output with no spread spectrum or frequency select pin Multifunction programmable pin: power-down, output enable, or frequency select pin Multifunction programmable pin: programmable clock output with spread spectrum or spread spectrum ON/OFF control pin Power supply ground Crystal output Description Crystal input or 1.8 V external clock input Document #: 001-12564 Rev. *F Page 3 of 14 CY25403/CY25423/CY25483 General Description Configurable PLLs The CY25403/CY25423/CY25483 have three programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having three PLLs is that a single device generates up to three independent frequencies from a single crystal. switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. PD#/OE Mode Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to operate as either frequency select (FS1), power-down (PD#) or output enable (OE) mode. PD# is a low-true input. If activated it shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. When this pin is programmed as output enable (OE), clock outputs can be enabled or disabled using OE (pin 5). Individual clock outputs can be programmed to be sensitive to this OE pin. Input Reference Clocks The input reference clock can be either a crystal or a clock signal, for CY25403/CY25423/CY25483. The input frequency range for crystal (XIN) is 8 MHz to 48 MHz and that for external reference clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the reference clock input CY25403/CY25423/CY25483 is 1.8 V. This gives user an option for this device to be compatible for different input clock voltage levels in the system. VDD Power Supply Options These devices have programmable power supply options. The CY25403/CY25423/CY25483 is a high voltage part that can be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V. Output Source Selection These devices have programmable input sources for each of its clock outputs. There are four available clock sources and these clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3. Output clock source selection is done by using four out of four crossbar switch. Thus, any one of these four available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to three independent clock outputs. Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Table 3 shows the typical rise and fall times for different drive strength settings. Table 3. Output Drive Strength Output Drive Strength Low Mid Low Mid High High Rise/Fall Time (ns) (Typical Value) 6.8 3.4 2.0 1.0 Spread Spectrum Control Two of the three PLLs (PLL2 and PLL3) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK3/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. Generic Configuration and Custom Frequency There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The device, CY25403/CY25423/CY25483 can be custom programmed to any desired frequencies and listed features. For customer specific programming, please contact local Cypress Field Application Engineer (FAE) or sales representative. Frequency Select Each PLL can be programmed for up to four different frequencies. There are two multifunction programmable pins, CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency select inputs, can be used to select among these arbitrarily programmed frequency settings. Each output has programmable output divider options. Glitch-Free Frequency Switch When the frequency select pin, FS(1:0) is used to switch frequency, the outputs are glitch-free provided frequency is Document #: 001-12564 Rev. *F Page 4 of 14 CY25403/CY25423/CY25483 Absolute Maximum Conditions Parameter VDD VIN TS ESDHBM UL-94 MSL Description Supply voltage for CY25403/CY25423/CY25483 – Input voltage for CY25403/CY25423/CY25483 Temperature, Storage ESD protection (human body model) Flammability rating Moisture sensitivity level Relative to VSS Non Functional JEDEC EIA/JESD22-A114-E V-0 at 1/8 in. SOIC package Condition Min –0.5 –0.5 –65 2000 – –3 10 Max 4.5 +150 Unit V °C Volts ppm – VDD+0.5 V Recommended Operating Conditions Parameter VDD TAC TAI CLOAD tPU Commercial ambient temperature Industrial ambient temperature Maximum load capacitance Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Description VDD operating voltage for CY25403/CY25423/CY25483 0 –40 – 0.05 Min 2.25 Typ – – -– – Max 3.60 +70 +85 15 500 Unit V °C °C pF ms Document #: 001-12564 Rev. *F Page 5 of 14 CY25403/CY25423/CY25483 DC Electrical Specifications Parameter VOL Description Output low voltage Conditions IOL = 2 mA, drive strength = [00] IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output high voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VIL1 VIL2 VIH1 VIH2 IIL IIH IILDN IIHDN RDN IDD[1,2 ] IDDS[1] CIN[1] Input low voltage of PD#/OE, FS0, FS1 and SSON Input low voltage of EXCLKIN Input high voltage of PD#/OE, FS0, FS1 and SSON Input high voltage of EXCLKIN for CY25403/CY25423/CY25483 Input low current, PD#/OE/FS1 Input high current, PD#/OE/FS1 Input low current, SSON and FS0 pins VIN = 0 V VIN = VDD VIN = 0 V (Internal pull-down resistor = 160k typ.) – – – – 0.2*VDD V 0.18 – 2.2 10 10 10 36 250 – – 7 V V V µA µA µA µA k mA µA pF VDD 0.4 – – V – Min – Typ Max 0.4 Unit V 0.8*VDD – 1.62 – – – 14 100 – – – – – – – – 160 22 3 – Input high current, SSON and FS0 pins VIN = VDD (Internal pull-down resistor = 160k typ.) Pull-down resistor of CLK1, CLK2/FS0 and CLK3/SSON pins Supply current for CY25403/CY25423/CY25483 Standby current Input capacitance Output clocks in off state by setting PD# = Low PD# = High, No load PD# = Low SSON, PD#/OE/FS1 and FS0 pins Notes 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. Document #: 001-12564 Rev. *F Page 6 of 14 CY25403/CY25423/CY25483 AC Electrical Specifications Parameter FIN (crystal) FIN (clock) FCLK DC DC TRF1 [3] Description Crystal frequency, XIN Input clock frequency (EXCLKIN) Output clock frequency Output duty cycle, all clocks except ref out Ref out duty cycle Output rise/fall time Conditions – – – Duty Cycle is defined in Figure 3 on page 8; t1/t2, measured at 50% of VDD Ref In Min 45%, Max 55% Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [00] Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [01] Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [10] Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [11] Configuration dependent. See Table Configuration Example for C-C Jitter Measured from 90% of the applied power supply level Min 8 8 3 45 40 – Typ – – – 50 – 6.8 Max 48 166 166 55 60 – Unit MH z MH z MH z % % ns TRF2[3] TRF3[3] TRF4[3] TCCJ[3, 4] TLOCK[3] Output rise/fall time – 3.4 – ns Output rise/fall time – 2.0 – ns Output rise/fall time – 1.0 – ns Cycle-to-cycle jitter (peak) PLL lock time – – 100 1 – 3 ps ms Configuration Example for C-C Jitter Ref. Frequency (MHz) 14.3181 19.2 27 48 CLK1 Output Freq. (MHz) 8.0 74.25 48 48 C-C Jitter Typ (ps) 134 99 67 93 CLK2 Output Freq. (MHz) 166 166 27 27 C-C Jitter Typ (ps) 103 94 109 123 CLK3 Output Freq. (MHz) 48 8 166 166 C-C Jitter Typ (ps) 92 91 103 137 Recommended Crystal Specification for SMD Package Parameter Fmin Fmax R1 C0 CL DL(max) Minimum frequency Maximum frequency Motional resistance (ESR) Shunt capacitance Parallel load capacitance Maximum crystal drive level Description Range 1 Range 2 Range 3 Unit 8 14 135 4 18 300 14 28 50 4 14 300 28 48 30 2 12 300 MHz MHz  pF pF µW Document #: 001-12564 Rev. *F Page 7 of 14 CY25403/CY25423/CY25483 Recommended Crystal Specification for Thru-Hole Package Parameter Fmin Fmax R1 C0 CL DL(max) Minimum frequency Maximum frequency Motional resistance (ESR) Shunt capacitance Parallel load capacitance Maximum crystal drive level Description Range 1 Range 2 Range 3 Unit 8 14 90 7 18 1000 14 24 50 7 12 1000 24 32 30 7 12 1000 MHz MHz  pF pF µW Test and Measurement Setup Figure 2. Test and Measurement Setup V DD 0.1  F DUT Outputs C LOAD GND Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 VDD 50% of VD D C lock O utput 0V Figure 4. Rise Time = TRF, Fall Time = TRF T RF T RF V DD 80% of V DD 20% of VDD 0V Clock Output Notes 3. Guaranteed by design but not 100% tested. 4. Configuration dependent. Document #: 001-12564 Rev. *F Page 8 of 14 CY25403/CY25423/CY25483 Ordering Information Part Number Pb-free CY25403SXC CY25403SXCT CY25423SXC CY25423SXCT CY25483SXC CY25483SXCT CY25403SXI CY25403SXIT CY25423SXI CY25423SXIT CY25483SXI CY25483SXIT Programmer CY3675-CLKMAKER1 CY3675-SOIC8A Programming Kit Socket Adapter Board, for programming CY25402, CY25403, CY25422, CY25423, CY25482, and CY25483 Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable Field Programmable 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C 1.8 V Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C 8-pin SOIC -Tape and Reel 1.8 V Type Package Supply Voltage Production Flow 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C 1.8 V Industrial, –40 °C to +85 °C Industrial, –40 °C to +85 °C 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C 8-pin SOIC -Tape and Reel 1.8 V 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for more information Possible Configurations Part Number[5] Pb-free CY25403/CY25423/CY254 8-pin SOIC 83SXC-xxx Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to +85 °C Industrial, –40 °C to +85 °C Type VDD(V) Production Flow CY25403/CY25423/CY254 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V 83SXC-xxxT CY25403/CY25423/CY254 8-pin SOIC 83SXI-xxx Supply Voltage: 2.5 V, 3.0 V, or 3.3 V CY25403/CY25423/CY254 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V 83SXI-xxxT Notes 5. xxx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative. Document #: 001-12564 Rev. *F Page 9 of 14 CY25403/CY25423/CY25483 Ordering Code Definitions CY254x3 SX C/I - xxx T Package Type: (T = Tape and Reel) Customer specific identification code Temperature code (C=Commercial or I=Industrial) 8-Pin SOIC package Marketing Code: CY25403/23/83 = Device Number Package Drawing and Dimensions Figure 5. 8-Pin (150-Mil) SOIC S8 51-85066 *E Document #: 001-12564 Rev. *F Page 10 of 14 CY25403/CY25423/CY25483 Acronyms Acronym DL DNU DUT EIA EMI ESD FAE FS JEDEC LVCMOS OE OSC PD PLL PPM SS SSC SSON Description drive level do not use device under test Electronic Industries Alliance electromagnetic interference electrostatic discharge field application engineer frequency select joint electron devices engineering council low voltage complementary metal oxide semiconductor output enable oscillator power-down phase-locked loop parts per million spread spectrum spread spectrum clock spread spectrum on Document #: 001-12564 Rev. *F Page 11 of 14 CY25403/CY25423/CY25483 Document Conventions Units of Measure Symbol Unit of Measure degree Celsius milliamperes megahertz milliseconds nanoseconds picofarad picoseconds volts microamperes C mA MHz ms ns pF ps V µA Document #: 001-12564 Rev. *F Page 12 of 14 CY25403/CY25423/CY25483 Document History Page Document Title: CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12564 REV. ** *A *B ECN NO. 690296 815788 1428744 Issue Date See ECN See ECN See ECN Orig. of Change RGL RGL New Data Sheet Minor Change: To post on web Description of Change RGL/AESA Changed data sheet format to match generic part, CY2544/46 Added new device and specification for high ref. input voltage part, CY7C1512KV18 Removed Preliminary from Title page Replaced CLK2 with REFOUT TSAI CXQ Posting to external web. Updated Ordering Information. Added note regarding Possible Configurations in Ordering Information section. Added Possible Configurations table for “xxx’ parts. Updated Package Drawing and Dimensions Updated Ordering Information and template. Updated to latest template Updated Package Drawing and Dimensions Added Units of Measure Added Contents *C *D 2748211 2899300 08/10/09 03/25/10 *E *F 2898568 3319132 06/02/10 07/18/11 CXQ BASH Document #: 001-12564 Rev. *F Page 13 of 14 CY25403/CY25423/CY25483 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-12564 Rev. *F Revised July 18, 2011 Page 14 of 14