CY2545QIT

CY2545/CY2547 Quad-PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface Quad-PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface Features ■ Four fully-integrated phase-locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ Wide operating output frequency range ❐ 3 to 166 MHz ■ ■ 24-pin QFN package ■ Commercial and industrial temperature ranges ■ One-time programmability For programming support, contact Cypress technical support or send an e-mail to clocks@cypress.com Benefits Serial programmable over two-wire I2C interface ■ Programmable spread spectrum with center and down spread option and Lexmark and Linear modulation profiles ■ VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V for CY2545 ❐ 1.8 V for CY2547 ■ Selectable output clock voltages independent of VDD supply: ❐ 1.8 V, 2.5 V, 3.0 V, and 3.3 V for CY2545 ❐ 1.8 V for CY2547 ■ Multiple high-performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ Application-specific programmable EMI reduction using spread spectrum for clocks ■ Programmable PLLs for system frequency margin tests ■ Meets critical timing requirements in complex system designs ■ Suitability for PC, consumer, portable, and networking applications ■ Power-down, output enable, or frequency select features ■ Low jitter, high accuracy outputs ■ Capable of zero PPM frequency synthesis error ■ Ability to synthesize nonstandard frequencies with Fractional-N capability ■ Uninterrupted system operation during clock frequency switch Up to eight clock outputs with programmable drive strength ■ Application compatibility in standard and low-power systems ■ ■ Glitch-free outputs while frequency switching Functional Description For a complete list of related documentation, click here. Logic Block Diagram CLKIN/RST Crossbar XIN/ EXCLKIN XOUT CLK1 Switch Output OSC PLL1 Bank 1 Dividers CLK3 and Drive PLL2 MUX and Control Logic FS SCL SDA Bank 2 Control CLK6 Bank 3 PLL3 (SS) CLK4 CLK5 Strength CLK7 CLK8 PLL4 (SS) I2C CLK2 PD#/OE SSON Cypress Semiconductor Corporation Document Number: 001-13196 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 2, 2017 CY2545/CY2547 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 4 Pinouts .............................................................................. 5 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 7 Four Configurable PLLs .............................................. 7 I2C Programming ........................................................ 7 Input Reference Clocks ............................................... 7 Multiple Power Supplies .............................................. 7 Output Bank Settings .................................................. 7 Output Source Selection ............................................. 7 Spread Spectrum Control ............................................ 7 Frequency Select ........................................................ 7 Glitch-Free Frequency Switch ..................................... 7 Device Reset Function ................................................ 7 PD#/OE Mode ............................................................. 7 Keep Alive Mode ......................................................... 7 Output Drive Strength .................................................. 8 Generic Configuration and Custom Frequency ........... 8 Output Driver Supply and Multi-Function Input Restriction ................................... 8 Serial I2C Programming Interface Protocol and Timing ......................................................... 9 Device Address ......................................................... 10 Data Valid .................................................................. 10 Data Frame ............................................................... 10 Acknowledge Pulse ................................................... 10 Write Operations ............................................................. 11 Writing Individual Bytes ............................................. 11 Writing Multiple Bytes ................................................ 11 Document Number: 001-13196 Rev. *I Read Operations ............................................................. 11 Current Address Read ............................................... 11 Random Read ........................................................... 11 Sequential Read ........................................................ 11 Serial I2C Programming Interface Timing Specifications .................................................... 11 Absolute Maximum Conditions ..................................... 12 Recommended Operating Conditions .......................... 12 DC Electrical Specifications .......................................... 13 AC Electrical Specifications .......................................... 14 Configuration Example .................................................. 14 Recommended Crystal Specification ........................... 15 Recommended Crystal Specification ........................... 15 Test and Measurement Setup ........................................ 16 Voltage and Timing Definitions ..................................... 16 Ordering Information ...................................................... 17 Possible Configurations ............................................. 17 Ordering Code Definitions ......................................... 17 Package Diagram ............................................................ 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC® Solutions ...................................................... 22 Cypress Developer Community ................................. 22 Technical Support ..................................................... 22 Page 2 of 22 CY2545/CY2547 Pinouts XIN/ EXCLKIN XOUT VDD CLKIN/RST CLK8 GND Figure 1. 24-pin QFN pinout 24 23 22 21 20 19 GND 1 18 GND CLK1 2 17 CLK7 VDD_CLK_B1 3 16 VDD_CLK_B3 15 CLK6/SSON 6 13 CLK5 7 8 9 10 11 12 GND VDD_CLK_B2 CLK4 14 CLK3/FS 5 SDA DNU SCL 4 GND PD#OE CLK2 Document Number: 001-13196 Rev. *I CY2545 24LD QFN Page 3 of 22 CY2545/CY2547 Pin Definitions CY2545 (24-pin QFN (VDD = 2.5 V, 3.0 V or 3.3 V Supply)) Pin No. Name I/O 1 GND Power Power supply ground Description 2 CLK1 Output Programmable clock output with spread spectrum. Output voltage depends on Bank1 voltage 3 VDD_CLK_B1 Power Power supply for Bank1 (CLK1, CLK2) output: 2.5 V/3.0 V/3.3 V and must be equal to or more than the VDD power supply. 4 PD#/OE Input Multifunction programmable pin: Output enable or Power-down mode 5 DNU DNU Do not use this pin 6 CLK2 Output Programmable clock output with spread spectrum. Output voltage depends on Bank1 voltage 7 GND Power Power supply ground 8 SCL Input Serial data clock 9 SDA 10 CLK3/FS Input/Output Serial data input/output 11 CLK4 Output Programmable clock output with no spread spectrum. Output voltage depends on Bank2 voltage 12 GND Power Power supply ground 13 CLK5 Output Programmable clock output with spread spectrum. Output voltage depends on Bank2 voltage Power Power supply for Bank2 (CLK3, CLK4, CLK5) output: 1.8 V/2.5 V/3.0 V/3.3 V Output/Input Multifunction programmable pin: Programmable clock output with no spread spectrum or frequency select input pin. Output voltage of CLK3 depends on Bank2 voltage 14 VDD_CLK_B2 15 CLK6/SSON 16 VDD_CLK_B3 Power Power supply for Bank3 (CLK6, CLK7, CLK8) output: 2.5 V/3.0 V/3.3 V 17 CLK7 Output Programmable clock output with spread spectrum. Output voltage depends on Bank3 voltage 18 GND Power Power supply ground 19 GND Power Power supply ground 20 CLK8 Output Programmable clock output with spread spectrum. Output voltage depends on Bank3 voltage 21 CLKIN/RST Input/Input Multifunction programmable pin. High true reset input or 2.5 V/3.0 V/3.3 V external reference clock input. The signal level of CLKIN input must track VDD power supply on pin 22. Output/Input Multifunction programmable pin: Programmable clock output with spread spectrum or spread spectrum ON/OFF control input pin. Output voltage of CLK6 depends on Bank3 voltage 22 VDD Power Power supply for core and inputs: 2.5 V/3.0 V/3.3 V 23 XOUT Output Crystal output 24 XIN/EXCLKIN Input Document Number: 001-13196 Rev. *I Crystal input or 1.8 V external clock input Page 4 of 22 CY2545/CY2547 Pinouts XIN/ EXCLKIN XOUT VDD CLKIN/RST CLK8 GND Figure 2. 24-pin QFN pinout 24 23 22 21 20 19 GND 1 18 GND CLK1 2 17 CLK7 VDD_CLK_B1 3 16 VDD_CLK_B3 PD#OE 4 15 CLK6/SSON VDD 5 14 VDD_CLK_B2 CLK2 6 13 CLK5 Document Number: 001-13196 Rev. *I CY2547 SCL SDA 10 11 12 GND 9 CLK4 8 CLK3/FS 7 GND 24LD QFN Page 5 of 22 CY2545/CY2547 Pin Definitions CY2547 (24-pin QFN (VDD = 1.8 V Supply)) Pin No. Name I/O 1 GND Power Power supply ground Description 2 CLK1 Output Programmable clock output with spread spectrum. Output voltage depends on Bank1 voltage 3 VDD_CLK_B1 Power Power supply for Bank1 (CLK1, CLK2) output: 1.8 V 4 PD#/OE Input Multifunction programmable pin: Output enable or Power-down mode 5 VDD Power Power supply for core and inputs: 1.8 V 6 CLK2 Output Programmable output clock with spread spectrum. Output voltage depends on Bank1 voltage 7 GND Power Power supply ground 8 SCL 9 SDA 10 CLK3/FS 11 CLK4 Input Serial data clock Input/Output Serial data input Output/Input Multifunction programmable pin: Programmable clock output with no spread spectrum or frequency select input pin. Output voltage of CLK3 depends on VDD_CLK_B2 voltage Output Programmable output clock with no spread spectrum. Output voltage depends on Bank2 voltage 12 GND Power Power supply ground 13 CLK5 Output Programmable clock output with spread spectrum. Output voltage depends on Bank2 voltage 14 VDD_CLK_B2 Power Power supply for Bank2 (CLK3, CLK4, CLK5) output: 1.8 V 15 CLK6/SSON 16 VDD_CLK_B3 Power Power supply for Bank3 (CLK6, CLK7, CLK8) output: 1.8 V 17 CLK7 Output Programmable clock output with spread spectrum. Output voltage depends on Bank3 voltage 18 GND Power Power supply ground 19 GND Power Power supply ground 20 CLK8 Output Programmable clock output with spread spectrum. Output voltage depends on Bank3 voltage 21 CLKIN/RST Input/Input Output/Input Multifunction programmable pin: Programmable clock output with spread spectrum or spread spectrum ON/OFF control input pin. Output voltage of CLK6 depends on VDD_CLK_B3 voltage Multifunction programmable pin: High true reset input or 1.8 V external low voltage reference clock input 22 VDD Power Power supply for core and inputs: 1.8 V 23 XOUT Output Crystal output 24 XIN/EXCLKIN Input Document Number: 001-13196 Rev. *I Crystal input or 1.8 V external clock input Page 6 of 22 CY2545/CY2547 Functional Overview Spread Spectrum Control The CY2545 and CY2547 have four I2C programmable PLLs available to generate output frequencies ranging from 3 to 166 MHz. The advantage of having four PLLs is that a single device generates up to four independent frequencies from a single crystal. Two sets of frequencies for each PLL can be programmed. This enables in system frequency switching using multifunction frequency select pin, FS. Two of the four PLLs (PLL3 and PLL4) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK7/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. I2C Programming Frequency Select Four Configurable PLLs 2 The CY2545 and CY2547 have a serial I C interface that programs the configuration memory array to synthesize output frequencies by programmable output divider, spread characteristics, drive strength, and crystal load capacitance. I2C can also be used for in system control of these programmable features. The device can store two different PLL frequency configurations, output source selection and output divider values for all eight outputs in its nonvolatile memory location. There is a multifunction programmable pin, CLK3/FS which, if programmed as frequency select input, can be used to select between these two arbitrarily programmed settings. Input Reference Clocks Glitch-Free Frequency Switch The input to the CY2545 and CY2547 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz. There is provision for two reference clock inputs, CLKIN and EXCLKIN with frequency range of 8 MHz to 166 MHz. For both devices, when CLKIN signal at pin 21 is used as a reference input, a valid signal at EXCLKIN (as specified in the AC and DC Electrical Specification table), must be present for the devices to operate properly. When the frequency select pin (FS) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is switched. Multiple Power Supplies The CY2545 and CY2547 are designed to operate at internal core supply voltage of 1.8 V. In the case of the high voltage part (CY2545), an internal regulator is used to generate 1.8 V from the 2.5 V/3.0 V/3.3 V VDD supply voltage at pin 22. For the low voltage part (CY2547), this internal regulator is bypassed and 1.8 V at VDD pin 22 is directly used. Output Bank Settings These devices have eight clock outputs grouped in three output driver banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2), (CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8), respectively. Separate power supplies are used for each of these banks and they can be any of 1.8 V, 2.5 V, 3.0 V, or 3.3 V for CY2545 and 1.8 V for CY2547 giving user multiple choice of output clock voltage levels. Device Reset Function There is a multifunction CLKIN/RST (pin 21) that can be programmed to use for the device reset function. There are two different programmable modes of operation for this device reset function. First one (called POR like reset), when used brings the device in the default register settings loosing all configuration changes made through the I2C interface. The second (called Clean Start), keeps the I2C programmed values while giving all outputs a simultaneous clean start from its low pull-down state. PD#/OE Mode PD#/OE (Pin 4) is programmable to operate as either power-down (PD#) or output enable (OE) mode. PD# is a low true input. If activated it shuts off the entire chip, resulting in minimum device power consumption. Setting this signal high brings the device into operational mode with default register settings. When this pin is programmed as output enable (OE), clock outputs are enabled or disabled using OE pin. Individual clock outputs can be programmed to be sensitive to this OE pin. Output Source Selection Keep Alive Mode These devices have eight clock outputs (CLK1 - 8). There are six available clock sources for these outputs. These clock sources are: XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source selection is done using four out of six crossbar switch. Thus, any one of these six available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to four independent clock outputs. By activating the device in the keep alive mode, power-down mode is changed to power saving mode. This disables all PLLs and outputs, but preserves the contents of the volatile registers. Thus, any configuration changes made through the I2C interface are preserved. By deactivating the keep alive mode, I2C memory is not preserved during power-down, but power consumption is reduced relative to the keep alive mode. Document Number: 001-13196 Rev. *I Page 7 of 22 CY2545/CY2547 Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Table 1 shows the typical rise and fall times for different drive strength settings. Table 1. Output Drive Strength Output Drive Strength Rise/Fall Time (ns) (Typical Value) Low 6.8 Mid Low 3.4 Mid High 2.0 High 1.0 Generic Configuration and Custom Frequency There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The device, CY2545/CY2547 can be custom programmed to any desired frequencies and listed features. For customer specific programming and I2C programmable memory bitmap definitions, contact your local Cypress Field Application Engineer (FAE) or sales representative. Document Number: 001-13196 Rev. *I Output Driver Supply and Multi-Function Input Restriction There are two programmable Output/Input function pins for CLK3/FS and CLK6/SSON. These are configurable as clock output or select input or spread spectrum ON/OFF control input pin. ■ When configured as Output, the driver supply voltage is defined by VDD_CLK_Bx and can be individually used with 1.8 V, 2.5 V, 3.0 V, or 3.3 V power supply apart from the VDD supply. ■ When configured as Input, the input threshold level is defined by VDD supply while the protection diode is connected to the respective VDD_CLK_Bx power supply. Therefore, if VDD_CLK_Bx is less than VDD – 0.5 V, a large leakage current would flow from the input pin to the VDD_CLK_Bx supply. The device does not permit this condition; it is required that the power supply for the bank (VDD_CLK_Bx) is more than VDD – 0.5 V. Example: In CY2545, if VDD_CLK_B2 = 1.8 V, CLK3/FS is configured as FS, and VDD = 3.3 V, there will be a leakage current from FS high to VDD_CLK_B2. The multi-function pin should only be used as clock output if the VDD_CLK_Bx is less than VDD – 0.5 V. In other words, when these multi-function programmable pins are configured as input, the power supply for the bank (VDD_CLK_Bx) should be more than VDD – 0.5 V. Page 8 of 22 CY2545/CY2547 Serial I2C Programming Interface Protocol and Timing The CY2545 and CY2547 use a 2-wire serial interface SDA and SCL that operates up to 400 kbits/s in read or write mode. The SDA and SCL timing and data transfer sequence is shown in Figure 3. The basic write serial format is: To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up and therefore, use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4. Figure 3. Data Transfer Sequence on the Serial Bus SCL SDA Address or Acknowledge Valid START Condition STOP Condition Data may be changed Figure 4. Data Frame Architecture SDA Write Multiple Contiguous Registers 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 8-bit Register Address (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH+1) 8-bit Register Data (XXH+2) 1 Bit Slave ACK 1 Bit Slave ACK 8-bit Register Data (FFH) 1 Bit Slave ACK 8-bit Register Data (00H) Stop Signal Start Signal SDA Read Current Address Read Start Signal SDA Read Multiple Contiguous Registers 1 Bit Slave ACK 1 Bit 1 Bit Slave R/W = 1 ACK 7-bit Device Address 1 Bit Slave ACK 1 Bit Master NACK 8-bit Register Data Stop Signal 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 8-bit Register Address (XXH) 1 Bit Master ACK 7-bit Device Address +R/W=1 8-bit Register Data (XXH) 1 Bit Master ACK 8-bit Register Data (XXH+1) 1 Bit Master ACK 8-bit Register Data (FFH) 1 Bit Master ACK 1 Bit Master ACK 1 Bit Master NACK 8-bit Register Data (00H) Stop Signal Start Signal Repeated Start bit Document Number: 001-13196 Rev. *I Page 9 of 22 CY2545/CY2547 Device Address Data Valid The device serial interface address is 69H. The device address is combined with a read/write bit as the LSB and is sent after each start bit. Data is valid when the clock is HIGH, and is only transitioned when the clock is LOW, as illustrated in Figure 5. Figure 5. Data Valid and Data Transition Periods SDAT tf tLOW tr tSU;DAT tf tHD;STA tr tBUF SCLK tHD;STA S tHD;DAT tHIGH tSU;STA tSU;STO Data Frame A start and stop sequence indicates every new data frame, as illustrated in Figure 6. Start Sequence - The start frame is indicated by SDA going LOW when SCL is HIGH. Every time a start signal is supplied, the next 8-bit data must be the device address (seven bits) and a R/W bit, S P Sr followed by register address (eight bits) and register data (eight bits). Stop Sequence - The stop frame is indicated by SDA going HIGH when SCL is HIGH. A stop frame frees the bus to go to another part on the same bus or to another random register address. Figure 6. Start and Stop Frame SDA Transition to next Bit START Acknowledge Pulse During write mode the CY2545/CY2547 responds with an acknowledge pulse after every eight bits. Do this by pulling the SDA line LOW during the N × 9th clock cycle as illustrated in SCL STOP Figure 7 (N = the number of bytes transmitted). During read mode, the master generates the acknowledge pulse after reading the data packet. Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data) SDA + START SCL DA6 DA5 DA0 + R/W + Document Number: 001-13196 Rev. *I ACK RA7 RA6 RA1 + + RA0 ACK D7 D6 D1 D0 ACK STOP + Page 10 of 22 CY2545/CY2547 Write Operations Writing Individual Bytes A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (ack = 0/LOW). The next eight bits must contain the data word intended for storage. After the data word is received, the slave responds with another acknowledge bit (ack = 0/LOW), and the master must end the write sequence with a STOP condition. read operation returns the value stored in location ‘n+1’. When the CY2545/CY2547 receive the slave address with the R/W bit set to a ‘1’, the CY2545/CY2547 issue an acknowledge and transmit the 8-bit word. The master device does not acknowledge the transfer, but generates a STOP condition, which causes the CY2545/CY2547 to stop transmission. Random Read To write multiple bytes at a time, the master does not end the write sequence with a STOP condition; instead, the master sends multiple contiguous bytes of data to be stored. After each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accepts data until the STOP condition responds to the acknowledge bit. When receiving multiple bytes, the CY2545 and CY2547 internally increment the register address. Through random read operations, the master may access any memory location. To perform this type of read operation, first the word address must be set. This is done by sending the address to the CY2545/CY2547 as part of a write operation. After sending the word address, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next, the master reissues the control byte with the R/W byte set to ‘1’. The CY2545/CY2547 then issue an acknowledge and transmit the 8-bit word. The master device does not acknowledge the transfer, but generates a STOP condition, which causes the CY2545/CY2547 to stop transmission. Read Operations Sequential Read Read operations are initiated the same way as write operations except that the R/W bit of the slave address is set to ‘1’ (HIGH). There are three basic read operations: current address read, random read, and sequential read. Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmitting the first 8-bit data word. This action increments the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master serially reads the entire contents of the slave device memory. When the internal address pointer points to the FFH register, after the next increment, the pointer points to the 00H register. Writing Multiple Bytes Current Address Read The CY2545 and CY2547 have an onboard address counter that retains 1 more than the address of the last word access. If the last word written or read was word ‘n’, then a current address Serial I2C Programming Interface Timing Specifications Parameter Description Min Max Unit – 400 kHz fSCLK Frequency of SCLK tHD:STA Hold time START condition 0.6 – s tLOW Low period of the SCLK clock 1.3 – s tHIGH High period of the SCLK clock 0.6 – s tSU:STA Setup time for a repeated START condition 0.6 – s tHD:DAT Data hold time 100 – ns tSU:DAT Data setup time 100 – ns tR Rise time – 300 ns tF Fall time – 300 ns tSU:STO Setup time for STOP condition 0.6 – s tBUF Bus-free time between STOP and START conditions 1.3 – s Document Number: 001-13196 Rev. *I Page 11 of 22 CY2545/CY2547 Absolute Maximum Conditions Parameter Description Condition Min Max Unit –0.5 4.5 V VDD Supply voltage for CY2545 VDD Supply voltage for CY2547 –0.5 2.6 V VDD_CLK_BX Output bank supply voltage –0.5 4.5 V VIN Input voltage for CY2545 Relative to VSS –0.5 VDD + 0.5 V VIN Input voltage for CY2547 Relative to VSS –0.5 2.2 V +150 °C TS Temperature and storage Nonfunctional –65 ESDHBM ESD protection (human body model) JEDEC EIA/JESD22-A114-E 2000 UL-94 Flammability rating V-0 at1/8 in. MSL Moisture sensitivity level V – 10 ppm Max Unit 3 Recommended Operating Conditions Parameter Description Min Typ VDD VDD operating voltage for CY2545 2.25 – 3.60 V VDD VDD operating voltage for CY2547 1.65 1.8 1.95 V VDD_CLK_BX Output driver voltage for bank 1, 2, and 3 for CY2545 1.43 – 3.60 V Output driver voltage for bank 1, 2, and 3 for CY2547 1.43 – 1.98 V TAC Commercial ambient temperature TAI Industrial ambient temperature CLOAD Maximum load capacitance tPU Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Document Number: 001-13196 Rev. *I 0 – +70 °C –40 – +85 °C – – 15 pF 0.05 – 500 ms Page 12 of 22 CY2545/CY2547 DC Electrical Specifications Parameter VOL Description Output low voltage Conditions IOL = 2 mA, drive strength = [00] Min Typ Max Unit – – 0.4 V VDD_CLK_BX – 0.4 – – V – – 0.4 V IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output high voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VOLSD Output low voltage, SDA VIL1 Input low voltage of PD#/OE, RST, FS, and SSON – – 0.2 × VDD V VIL2 Input low voltage of CLKIN for CY2545 – – 0.2 × VDD V VIL3 Input low voltage of EXCLKIN for CY2545 – – 0.3 V VIL4 Input low voltage of CLKIN, EXCLKIN for CY2547 – – 0.2 × VDD V VIH1 Input high voltage of PD#/OE, RST, FS, and SSON 0.8 × VDD – – V VIH2 Input high voltage of CLKIN for CY2545 0.8 × VDD – – V VIH3 Input high voltage of EXCLKIN for CY2545 1.62 – 2.2 V VIH4 Input high voltage of CLKIN, EXCLKIN for CY2547 0.8 × VDD – – V IILPD Input low current of RST and PD#/OE VIL = 0 V – – 10 µA IIHPD Input high current of RST and PD#/OE VIH = VDD – – 10 µA IILSR Input low current of SSON and FS VIL = 0 V (Internal pull-down = 160 k typ) – – 10 µA IIHSR Input high current of SSON and FS 14 – 36 µA RDN Pull-down resistor of (CLK1-CLK8) when off, CLK6/SSON and CLK3/FS 100 160 250 k IDD[1, 2] Supply current for CY2547 PD# = high, no load – 20 – mA IOL = 4 mA VIH = VDD (Internal pull-down = 160 k typ) Supply current for CY2545 PD# = high, no load – 22 – mA IDDS[1] Standby current PD# = low, no load, with I2C circuit not in keep alive mode – 3 – µA IPD[1] Power-down current PD# = low, no load, with I2C circuit in keep alive mode – – 1 mA CIN[1] Input capacitance SSON, RST, PD#/OE or FS inputs – 7 pF Notes 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. Document Number: 001-13196 Rev. *I Page 13 of 22 CY2545/CY2547 AC Electrical Specifications Parameter Description FIN (crystal) Crystal frequency, XIN FIN (clock) Input clock frequency FCLK Output clock frequency Conditions Min Typ Max Unit 8 – 48 MHz Clock inputs CLKIN or EXCLKIN 8 – 166 MHz CY2545 (VDD_CLK_Bx = 2.5 V, 3.0 V, 3.3 V) and CY2547 3 – 166 MHz CY2545 (VDD_CLK_Bx = 1.8 V) 3 – 50 MHz DC1 Output duty cycle, all clocks Duty cycle is defined in Figure 9; t1/t2, except ref out measured 50% of VDD 45 50 55 % DC2 Ref out clock duty cycle Ref In Min 45%, Max 55% 40 – 60 % TRF1[3] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [00] – 6.8 – ns TRF2[3] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [01] – 3.4 – ns TRF3[3] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [10] – 2.0 – ns TRF4[3] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [11] – 1.0 – ns TCCJ[3, 4] Cycle-to-cycle jitter max (Pk-Pk) Configuration dependent. See Configuration Example – 150 – ps TLOCK[3] PLL lock time Measured from 90% of the applied power supply level – 1 3 ms Configuration Example For C-C Jitter Ref. Freq. (MHz) CLK1 Output CLK2 Output CLK3 Output CLK4 Output Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) 14.3181 8.0 134 166 103 48 92 74.25 81 19.2 74.25 99 166 94 8 91 27 110 27 48 67 27 109 166 103 74.25 97 48 48 93 27 123 166 137 166 138 CLK5 Output Freq. (MHz) C-C Jitter Typ (ps) Not used 48 75 Not used 8 103 Notes 3. Guaranteed by design but not 100% tested. 4. Configuration dependent. Document Number: 001-13196 Rev. *I Page 14 of 22 CY2545/CY2547 Recommended Crystal Specification For SMD Package Parameter Description Range 1 Range 2 Range 3 Unit Fmin Minimum frequency 8 14 28 MHz Fmax Maximum frequency 14 28 48 MHz R1 Motional resistance (ESR) 135 50 30  C0 Shunt capacitance 4 4 2 pF CL Parallel load capacitance 18 14 12 pF DL(max) Maximum crystal drive level 300 300 300 µW Range 1 Range 2 Range 3 Unit Recommended Crystal Specification For Thru-Hole Package Parameter Description Fmin Minimum frequency 8 14 24 MHz Fmax Maximum frequency 14 24 32 MHz R1 Motional resistance (ESR) 90 50 30  C0 Shunt capacitance 7 7 7 pF CL Parallel load capacitance DL(max) Maximum crystal drive level Document Number: 001-13196 Rev. *I 18 12 12 pF 1000 1000 1000 µW Page 15 of 22 CY2545/CY2547 Test and Measurement Setup Figure 8. Test and Measurement Setup V DD 0.1 F Outputs C LOAD DUT GND Voltage and Timing Definitions Figure 9. Duty Cycle Definition t1 t2 VDD_CLK_BX 50% of V Clock Output DD_CLK_BX 0V Figure 10. Rise Time = TRF, Fall Time = TRF TRF TRF V DD_CLK_BX 80% of V Clock Output Document Number: 001-13196 Rev. *I 20% of V 0V DD_CLK_BX DD_CLK_BX Page 16 of 22 CY2545/CY2547 Ordering Information Part Number Type Package Supply Voltage (VDD) Production Flow Pb-free CY2547QI Field Programmable 24-pin QFN 1.8 V Industrial, –40 °C to +85 °C CY2547QIT Field Programmable 24-pin QFN – Tape and Reel 1.8 V Industrial, –40 °C to +85 °C Products are also offered as factory programmed customer specific devices with customized part numbers. The Possible Configurations shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales representative for more information. Possible Configurations Part Number Type Package Supply Voltage (VDD) Production Flow Pb-free CY2545QCxxx Factory Configured 24-pin QFN 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to +70 °C CY2545QCxxxT Factory Configured 24-pin QFN – Tape and Reel 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to +70 °C CY2547QCxxx Factory Configured 24-pin QFN 1.8 V Commercial, 0 °C to +70 °C CY2547QCxxxT Factory Configured 24-pin QFN – Tape and Reel 1.8 V Commercial, 0 °C to +70 °C CY2545QIxxx Factory Configured 24-pin QFN 2.5 V, 3.0 V or 3.3 V Industrial, –40 °C to +85 °C CY2545QIxxxT Factory Configured 24-pin QFN – Tape and Reel 2.5 V, 3.0 V or 3.3 V Industrial, –40 °C to +85 °C CY2547QIxxx Factory Configured 24-pin QFN 1.8 V Industrial, –40 °C to +85 °C CY2547QIxxxT Factory Configured 24-pin QFN – Tape and Reel 1.8 V Industrial, –40 °C to +85 °C Ordering Code Definitions CY 2545Q/2547Q C/I xxx T Tape and reel Three digit numeric custom configuration code Temperature range: C = Commercial, I = Industrial Base part number Company Code: CY = Cypress Document Number: 001-13196 Rev. *I Page 17 of 22 CY2545/CY2547 Package Diagram Figure 11. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A (2.65 × 2.65 E-Pad (Sawn)) Package Outline, 001-13937 001-13937 *F Document Number: 001-13196 Rev. *I Page 18 of 22 CY2545/CY2547 Acronyms Document Conventions Table 2. Acronyms Used in this Document Units of Measure Acronym Description Table 3. Units of Measure EIA Electronic Industries Alliance ESD Electrostatic Discharge C ESR Symbol Units of Measure degree Celsius Equivalent Series Resistance kHz kilohertz I2C Inter Integrated Circuit MHz megahertz JEDEC Joint Electron Device Engineering Council A microampere PLL Phase-Locked Loop s microsecond Quad Flat No-lead W microwatt mA milliampere ms millisecond ns nanosecond W ohm ppm parts per million % percent QFN Document Number: 001-13196 Rev. *I pF picofarad ps picosecond V volt W watt Page 19 of 22 CY2545/CY2547 Document History Page Document Title: CY2545/CY2547, Quad-PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface Document Number: 001-13196 Revision ECN Orig. of Change Submission Date ** 870780 RGL / AESA 03/23/2007 New data sheet. *A 1504843 RGL / AESA 10/03/2007 Replaced VDD_CORE with VDD in all instances across the document. Updated Serial I2C Programming Interface Timing Specifications: Changed minimum value of tSU parameter from 100 ns to 250 ns. Updated Absolute Maximum Conditions: Replaced “MIL-STD-883, Method 3015” with “JEDEC EIA/JESD22-A114-E” in “Conditions” column of ESDHBM parameter. Updated Recommended Operating Conditions: Updated all details of VDD parameter (Combined three rows into one row for CY2545). *B 2899681 CXQ 03/26/2010 Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85203 – Changed revision from *A to *B. *C 3302754 CXQ 07/05/2011 Added Ordering Code Definitions under Ordering Information. Added Acronyms and Units of Measure. Updated to new template. *D 4401186 AJU 06/06/2014 Updated Package Diagram: spec 51-85203 – Changed revision from *B to *D. Updated to new template. Completing Sunset Review. *E 4586478 TAVA 12/03/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Serial I2C Programming Interface Protocol and Timing: Updated Figure 4 (Updated the last ACK in SDA Read-Current Address Read and SDA Read-Multiple Contiguous Registers to “NACK”). *F 5140921 TAVA 03/14/2016 Updated Serial I2C Programming Interface Protocol and Timing: Updated Data Valid: Updated Figure 5. Updated Serial I2C Programming Interface Timing Specifications: Updated all details. Updated Ordering Information: Updated part numbers. Updated Ordering Code Definitions. Updated Package Diagram: Removed spec 51-85203 *D. Added spec 001-13937 *F. Updated to new template. *G 5475518 BPIN 10/14/2016 Updated Ordering Information: Updated part numbers. Updated to new template. Document Number: 001-13196 Rev. *I Description of Change Page 20 of 22 CY2545/CY2547 Document History Page (continued) Document Title: CY2545/CY2547, Quad-PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface Document Number: 001-13196 Revision ECN Orig. of Change Submission Date Description of Change *H 5778174 PSR 06/19/2017 Updated Features: Added one-time programmability. Updated Pin Definitions: Updated details in “Description” column corresponding to pin numbers 2, 6, 11, 13, 17, and 20. Updated Pin Definitions: Updated details in “Description” column corresponding to pin numbers 2, 6, 11, 13, 17, and 20. Updated Functional Overview: Added Output Driver Supply and Multi-Function Input Restriction. Updated to new template. *I 5955034 XHT 11/02/2017 Updated DC Electrical Specifications: Updated details in “Max” column corresponding to VIL2, VIL3, and VIL4 parameters. Updated details in “Min” column corresponding to VIH2, and VIH4 parameters. Updated to new template. Document Number: 001-13196 Rev. *I Page 21 of 22 CY2545/CY2547 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2007–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-13196 Rev. *I Revised November 2, 2017 Page 22 of 22