CY26114KZC

CY26114 One-PLL Clock Generator Features Benefits ■ Integrated phase-locked loop ■ Internal PLL with up to 333 MHz internal operation. ■ Low skew, low jitter, high accuracy outputs ■ Meets critical timing requirements in complex system designs. ■ 3.3V operation with 2.5 V output option ■ Enables application compatibility. Part Number Outputs Input Frequency CY26114 4 25 MHz Crystal Input Output Frequency Range 2 copies of 100 MHz, 1 copy of 50 MHz, 1 copy 25, 33, 50, and 66 MHz (frequency selectable) Logic Block Diagram XIN Q OSC. Φ VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P 100MHz 100MHz PLL 50MHz (frequency selectable) 25/33/50/66MHz FS0 FS1 VDDL VDD AVDD AVSS VSS VSSL CLK4 Frequency Select Options FS1 FS0 CLK 4 Units 0 0 25 MHz 0 1 33 MHz 1 0 50 MHz 1 1 66 MHz Cypress Semiconductor Corporation Document #: 38-07098 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 15, 2008 [+] Feedback CY26114 Pin Configurations Figure 1. CY26114, 16-Pin TSSOP XIN VDD 1 16 XOUT 2 15 AVDD FS0 3 14 4 13 CLK4 CLK3 VSS AVSS 5 12 N/C VSSL 6 11 VDDL LCLK1 LCLK2 7 10 FS1 8 9 N/C Table 1. Pin Definitions Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply AVDD 3 Analog Voltage Supply FS0 4 Frequency Select 0 AVSS 5 Analog Ground VSSL 6 LCLK Ground LCLK1 7 100 MHz Output clock at VDDL Level LCLK2 8 100 MHz Output clock at VDDL Level N/C 9 No Connect FS1 10 Frequency Select 1 VDDL 11 LCLK Voltage Supply (2.5V or 3.3V) N/C 12 No Connect VSS 13 Ground CLK3 14 50 MHz Output Clock CLK4 15 25, 33, 50, and 66 MHz Clock Output (frequency selectable) XOUT[1] 16 Reference Crystal Output Note 1. Float XOUT if XIN is externally driven. Document #: 38-07098 Rev. *B Page 2 of 5 [+] Feedback CY26114 Absolute Maximum Conditions Parameter VDD VDDL TJ Description Supply Voltage IO Supply Voltage Junction Temperature Digital Inputs Digital Outputs Referred to VDD Digital Outputs Referred to VDDL Electro-Static Discharge Min –0.5 AVSS – 0.3 VSS – 0.3 VSS – 0.3 2 Max 7.0 7.0 125 AVDD + 0.3 VDD + 0.3 VDDL +0.3 Unit V V °C V V V kV Recommended Operating Conditions Parameter VDD VDDL TA CLOAD fREF tPU Description Operating Voltage Operating Voltage Ambient Temperature Maximum Load Capacitance Reference Frequency Power Up Time—for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min 3.0 2.375 0 Typ 3.3 2.5 Max 3.6 2.625 70 15 25 0.05 500 Unit V V °C pF MHz ms DC Electrical Characteristics Parameter[2] IOH IOL IOH IOL VIH VIL IVDD IVDDL IVDDL Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Supply Current Description VOH = VDD – 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VOH = VDDL – 0.5, VDDL=2.5V VOL = 0.5, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current (VDDL = 3.6V) VDDL Current (VDDL = 2.625V) Min 12 12 8 8 0.7 Typ 24 24 16 16 Max 0.3 25 20 15 Unit mA mA mA mA VDD VDD mA mA mA Max 55 Unit % AC Electrical Characteristics Parameter[2] Name DC Output Duty Cycle t3 Rising Edge Rate t3 Rising Edge Rate t4 Falling Edge Rate t4 Falling Edge Rate t5 t9 t10 Skew Clock Jitter PLL Lock Time Description Duty cycle is defined in Figure 2; t1/t2, 50% of VDD Output clock rise time, 20%–80% of VDD/VDDL = 3.3V Output clock rise time, 20%–80% of VDDL = 2.5V Output clock fall time, 80%–20% of VDD/VDDL = 3.3V Output clock fall time, 80%–20% of VDDL = 2.5V Delay between related outputs at rising edge Peak to peak period jitter Min 45 Typ 50 0.8 1.4 V/ns 0.6 1.2 V/ns 0.8 1.4 V/ns 0.6 1.2 V/ns 250 200 3 ps ps ms Note 2. Not 100% tested. Document #: 38-07098 Rev. *B Page 3 of 5 [+] Feedback CY26114 Figure 2. Duty Cycle Definitions: DC = t2/t1 t1 t2 CLK 50% 50% Figure 3. Rise Time and Fall Time Definitions t3 t4 80% CLK 20% Figure 4. Test Circuit VDD 0.1 μF OUTPUTS CLK out CLOAD AVDD 0.1 μF GND Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26114ZC[3] Z16 16-Pin TSSOP Commercial 3.3V CY26114KZC Z16 16-Pin TSSOP Commercial 3.3V CY26114KZCT Z16 16-Pin TSSOP- Tape and Reel Commercial 3.3V Note 3. Not recommended for new designs. Document #: 38-07098 Rev. *B Page 4 of 5 [+] Feedback CY26114 Document History Page Document Title: CY26114 One-PLL Clock Generator Document Number: 38-07098 Revision ECN No. Origin of Change Submission Date ** 107333 CKN 12/14/02 Description of Change New Data Sheet *A 121867 RBI 08/28/01 Power up requirements added to Operating Conditions Information *B 2441946 AESA 05/15/08 Updated template. Added Note “Not recommended for new designs.” Added part number CY26114KZC, and CY26114KZCT in ordering information table. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. 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Document #: 38-07098 Rev. *B Revised May 15, 2008 Page 5 of 5 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback