CY28441
Clock Generator for Intel Alviso Chipset
Features
• 33-MHz PCI clock
• Low-voltage frequency select input
• Compliant to Intel CK410M
• I2C support with readback capabilities
• Supports Intel Pentium®-M CPU
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Selectable CPU frequencies
• Differential CPU clock pairs
• 3.3V power supply
• 100-MHz differential SRC clocks
• 56-pin TSSOP package
• 96-MHz differential dot clock
• 48-MHz USB clocks
• SRC clocks independently stoppable through
CLKREQ#[A:B]
CPU
SRC
PCI
REF
DOT96
USB_48
x2 / x3
x6 / x7
x6
x1
x1
x1
Block Diagram
XIN
XOUT
CPU_STP#
PCI_STP#
CLKREQ[A:B]#
XTAL
OSC
PLL1
Pin Configuration
VDD_REF
REF
PLL Ref Freq
Divider
Network
FS_[C:A]
VTT_PWRGD#
IREF
PD
PLL2
SDATA
SCLK
I2C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY28441
VDD_PCI
VSS_PCI
PCI3
VDD_CPU
PCI4
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
PCI5
VDD_SRC
VSS_PCI
SRCT[0:5], SRCC[0:5]
VDD_PCI
PCIF0/ITP_EN
PCIF1
VTT_PWRGD#/PD
VDD_PCI
VDD_48
PCI[2:5]
USB_48/FS_A
VDD_PCIF
VSS_48
PCIF[0:1]
DOT96T
DOT96C
VDD_48 MHz
FS_B/TEST_MODE
DOT96T
SRCT0
DOT96C
SRCC0
USB_48
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRC4_SATAT
SRC4_SATAC
VDD_SRC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2
PCI_STP#
CPU_STP#
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
CLKREQA#
CLKREQB#
SRCT5
SRCC5
VSS_SRC
56 TSSOP
Cypress Semiconductor Corporation
Document #: 38-07679 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 13, 2004
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CY28441
Pin Description
Pin No.
Name
Type
Description
33, 32
CLKREQA#,
CLKREQB#,
I, PU
3.3V LVTTL input for enabling assigned SRC clock, active LOW. CLKREQA#
defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable
SRCT/C5. Assignment can be changed via SMBUS register Byte 8.
54
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
44, 43, 41, 40 CPUT/C
O, DIF Differential CPU clock outputs.
36, 35
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
14, 15
DOT96T, DOT96C
O, DIF Fixed 96-MHz clock output.
12
FS_A/USB_48
I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications.
16
FS_B/TEST_MODE
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications.
53
FS_C/TEST_SEL
I
3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled
to greater than 2.0V when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications.
39
IREF
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
56, 3, 4, 5
PCI
O, SE 33-MHz clocks.
55
PCI_STP#
I, PU
8
PCIF0/ITP_EN
I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1
O, SE 33-MHz clock.
52
REF
O, SE Reference clock. 3.3V 14.318-MHz clock output.
46
SCLK
I
47
SDATA
I/O
26, 27
SRC4_SATAT,
SRC4_SATAC
24, 25, 22,
SRCT/C
23, 19, 20,
17, 18, 31, 30
11
3.3V LVTTL input for PCI_STP# active LOW.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Differential serial reference clocks.
VDD_48
PWR
3.3V power supply for outputs.
42
VDD_CPU
PWR
3.3V power supply for outputs.
1,7
VDD_PCI
PWR
3.3V power supply for outputs.
48
VDD_REF
PWR
3.3V power supply for outputs.
21, 28, 34
VDD_SRC
PWR
3.3V power supply for outputs.
37
VDDA
PWR
3.3V power supply for PLL.
13
VSS_48
GND
Ground for outputs.
45
VSS_CPU
GND
Ground for outputs.
2,6
VSS_PCI
GND
Ground for outputs.
51
VSS_REF
GND
Ground for outputs.
29
VSS_SRC
GND
Ground for outputs.
38
VSSA
GND
Ground for PLL.
10
VTT_PWRGD#/PD
Document #: 38-07679 Rev. **
I
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active LOW) assertion, this pin becomes a real-time input for asserting
power-down (active HIGH).
Page 2 of 20
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CY28441
Pin Description
Pin No.
Name
50
XIN
49
XOUT
Type
I
Description
14.318-MHz crystal input.
O, SE 14.318-MHz crystal output.
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode. See Table 1.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operations from the controller.
For Block Write/Read operation, the bytes must be accessed
in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte
has been transferred. For Byte Write and Byte Read operations, the system controller can access individually indexed
bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 2.
The Block Write and Block Read protocol is outlined in Table 3
while Table 4 outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
FS_B
FS_A
CPU
SRC
PCIF/PCI
REF0
DOT96
USB
1
0
1
100 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
0
1
1
0
1
0
0
0
0
1
0
0
1
1
0
1
1
1
RESERVED
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block Read or Block Write operation, 1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Slave address – 7 bits
Block Read Protocol
Bit
1
8:2
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
Document #: 38-07679 Rev. **
Page 3 of 20
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CY28441
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
27:20
28
36:29
37
45:38
Block Read Protocol
Description
Bit
Byte Count – 8 bits
20
Acknowledge from slave
27:21
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N –8 bits
....
Acknowledge from slave
....
Stop
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
37:30
46
Description
Repeat start
38
46:39
47
55:48
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Byte Read Protocol
Description
Bit
Start
1
Slave address – 7 bits
8:2
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Data byte – 8 bits
20
28
Acknowledge from slave
29
Stop
27:21
Repeated start
Slave address – 7 bits
28
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
7
1
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
6
1
RESERVED
5
1
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4
1
SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3
1
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Document #: 38-07679 Rev. **
Description
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED
Page 4 of 20
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CY28441
Byte 0:Control Register 0 (continued)
Bit
@Pup
Name
Description
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0
1
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
7
1
PCIF0
Description
6
1
DOT_96T/C
5
1
USB_48
4
1
REF
3
0
Reserved
Reserved
2
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
0
0
CPUT/C
SRCT/C
PCIF
PCI
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI
PCI Output Drive strength
0 = Low drive 1 = High drive
2
1
Reserved
Reserved, Set = 1
1
1
Reserved
Reserved, Set = 1
0
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
0
RESERVED
5
0
SRC5
Document #: 38-07679 Rev. **
RESERVED
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Page 5 of 20
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CY28441
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC3
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0
0
SRC0
Allow control of SRC[T/C]0 with assertion of PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit
@Pup
Name
7
0
Reserved
Reserved, Set = 0
Description
6
0
DOT96T/C
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
0
Reserved
4
0
PCIF1
Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
CPU[T/C]2
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
1
CPU[T/C]1
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU[T/C]0
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Reserved, Set = 0
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
5
0
CPU[T/C]1
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
4
0
CPU[T/C]0
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
3
0
SRC[T/C][7:0]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 6: Control Register 6
Bit
@Pup
7
0
Document #: 38-07679 Rev. **
Name
Description
REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N Clock
Page 6 of 20
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CY28441
Byte 6: Control Register 6 (continued)
Bit
@Pup
Name
Description
6
0
5
0
Reserved
4
1
REF
3
1
PCIF, SRC, PCI
2
Externally
selected
CPUT/C
FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
1
Externally
selected
CPUT/C
FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
0
Externally
selected
CPUT/C
FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Hi-Z mode,
Reserved, Set = 0
REF Output Drive Strength
0 = 1X, 1 = 2X
SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
Revision Code Bit 3
6
0
Revision Code Bit 2
Revision Code Bit 2
5
0
Revision Code Bit 1
Revision Code Bit 1
4
0
Revision Code Bit 0
Revision Code Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
BYTE 8: CLKREQ Control Register
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
1
CLKREQ#B
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
5
0
CLKREQ#B
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
4
0
CLKREQ#B
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
3
0
Reserved
Reserved
2
1
CLKREQ#A
SRC[T/C]4 CLKREQ#A control
1 = SRC[T/C]4 stoppable by CLKREQ#A pin
0 = SRC[T/C]4 not controlled by CLKREQ#A pin
1
0
CLKREQ#A
SRC[T/C]2 CLKREQ#A control
1 = SRC[T/C]2 stoppable by CLKREQ#A pin
0 = SRC[T/C]2 not controlled by CLKREQ#A pin
0
0
CLKREQ#A
SRC[T/C]0 CLKREQ#A control
1 = SRC[T/C]0 stoppable by CLKREQ#A pin
0 = SRC[T/C]0 not controlled by CLKREQ#A pin
Document #: 38-07679 Rev. **
Page 7 of 20
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CY28441
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
Crystal Recommendations
Clock Chip
The CY28441 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28441 to
operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading. See Table 5.
Pin
3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Ci2
Ci1
X2
X1
Cs1
Cs2
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Figure 1. Crystal Capacitive Clarification
Total Capacitance (as seen by the crystal)
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[0:1]# Description
The CLKREQ#[A:B] signals are active LOW input used for
clean enabling and disabling selected SRC outputs. The
outputs controlled by CLKREQ#[A:B] are determined by the
settings in register byte 8. The CLKREQ# signal is a
de-bounced signal in that it’s state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or de-assertion. (The assertion and
deassertion of this signal is absolutely asynchronous.)
Document #: 38-07679 Rev. **
Page 8 of 20
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CY28441
.
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the assertion to active outputs is between 2-6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs will be driven HIGH
within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater
than 200 mV.
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ#[A:B] pins is all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ#[A:B] are to be stopped after their
next transition. The final state of all stopped DIF signals is
LOW, both SRCT clock and SRCC clock outputs will not be
driven.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held low on their next
HIGH to LOW transition and differential clocks must held HIGH
or Hi-Zd (depending on the state of the control register drive
mode bit) on the next diff clock# HIGH to LOW transition within
4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tristate.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tristate. Note Figure 4 shows
CPUT = 133 MHz and PD drive mode = ‘1’ for all differential
outputs. This diagram and description is applicable to valid
CPU frequencies 100 and 133 MHz. In the event that PD mode
is desired as the initial power-on state, PD must be asserted
HIGH in less than 10 µs after asserting Vtt_PwrGd#.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
Document #: 38-07679 Rev. **
Page 9 of 20
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CY28441
Tstable
200mV
Figure 7. CPU_STP# Deassertion Waveform
1.8mS
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z
Document #: 38-07679 Rev. **
Page 11 of 20
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CY28441
PCI_STP# Assertion[1]
PCI_STP# Deassertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transitions to a high level. (See Figure 11.)
PCI_STP#
Tsu
PCI_F
PCI
SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
Note:
1. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 55 and the other is SMBus byte6 bit 3. These two inputs are logically
OR’ed. If either the external pin or the internal SMBus register bit is set LOW then the stoppable PCI clocks will be stopped in a logic LOW state.
Document #: 38-07679 Rev. **
Page 12 of 20
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CY28441
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
State 0
Clock State
W ait for
VTT_PW RGD#
State 1
State 2
Off
Clock Outputs
State 3
On
On
Off
Clock VCO
Device is not affected,
VTT_PW RGD# is ignored
Sample Sels
Figure 12. VTT_PWRGD# Timing Diagram
S2
S1
Delay
>0.25mS
VTT_PWRGD# = Low
Sample
Inputs straps
VDD_A = 2.0V
Wait for