CY28510

510 CY28510 Peripheral I/O Clock Generator Features • 15 33.27-MHz or 66.669-MHz clock outputs • 1 REF 14.318 MHz • Divide by 2, spread spectrum and output enable all selectable on a per-output basis via I2C register bits • Divide by 2 mode default values strappable on a per-group basis • Output Enable pin controls all outputs • I2C Compatible Programmability With Block and Byte Modes • I2C Operates Up to 1MHz • I2C Address Selection of D0, D2, D4 or D6 • 48 Pin SSOP Package Block Diagram XIN REF Pin Configuration Mux Mux PLL 1with Spread Spectrum Mux ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 CLKG0_0 CLKG0_1 CLKG0_2 CLKG0_3 CLKG0_4 CLKG0_5 CLKG0_6 CLKG0_7 CLKG1_0 CLKG1_1 CLKG1_2 CLKG1_3 CLKG2_0 CLKG2_1 CLKG3 66MHz Mux Mux Mux Mux (Group Frequency Select, 33 or 66MHz) Mux CLK_STOP# PLL 2 no Spread Spectrum 66MHz GFS0 Mux SCLK SDATA ADDSEL(0:1) I2C Mux Mux Mux GFS3 REF GFS0 VDDX VSSX XIN XOUT VDDC ADDSEL0 ADDSEL1 VSSC C LK_STOP# SCLK SDATA GFS1 GFS2 OE CLKG3 VDDQ3 VSSQ3 VSSQ2 CLKG2_1 CLKG2_0 VDDQ2 GFS1 Mux 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ0 CLKG0_0 CLKG0_1 VSSQ0 CLKG0_2 VDDQ0 VSSQ0 CLKG0_3 CLKG0_4 VDDQ0 CLKG0_5 CLKG0_6 CLKG0_7 VSSQ0 VDDQ1 CLKG1_0 CLKG1_1 VSSQ1 VDDQ1 CLKG1_2 CLKG1_3 VSSQ1 VDDA VSSA CY28510 Mux GFS2 Mux GFS3 OE Cypress Semiconductor Corporation Document #: 38-07542 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 28, 2003 CY28510 Pin Description Pin 2 6 Name REF XIN Type O I Power VDDX VDDX Description Reference Clock: 3.3V 14.318-MHz clock output. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection for an external 14.318-MHz crystal output. I2C address selection. ADDSEL1, ADSEL0: 0,0 = D0; 0,1 = D2, 1,0 = D4, 1,1 = D6 7 9 10 12 13 14 3 15 16 1 17 18 22,23 28,29,32,33 36,37,38,40,4 1,44,46,47 39 43 48 35 42 45 30 37 34 31 24 21 19 20 XOUT ADDSEL0 ADDSEL1 CLK_STOP# SCLK SDATA GFS0 GFS1 GFS2 GFS3 OE CLKG3 CLKG2_(1:0) CLKG1_(3:0) CLKG0_(7:0) VDDQ0_2 VDDQ0_1 VDDQ0_0 VSSQ0 VSSQ0 VSSQ0 VDDQ1 VSSQ1 VDDQ1 VSSQ1 VDDQ2 VSSQ2 VDDQ3 VSSQ3 O I, PU 250 KΩ I, PU 250 KΩ I, PU 250 KΩ I I/O I, PD 250 KΩ I, PD 250 KΩ I, PD 250 KΩ I, PD 250 KΩ I, PU 250 KΩ O O O O PWR PWR PWR GND GND GND PWR GND PWR GND PWR GND PWR GND VDDX VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VSSQ3 VSSQ2 VSSQ1 VSSQ0 Synchronous clock stop pin. When low, all of the clocks except REF are stopped low after completing a normal positive pulse cycle. I2C compatible SCLOCK. I2C compatible SDATA. Group frequency select 0. 0 = 33 MHz, 1 = 66 MHz. Group frequency select 1. 0 = 33 MHz, 1 = 66 MHz. Group frequency select 2. 0 = 33 MHz, 1 = 66 MHz. Group frequency select 3. 0 = 33 MHz, 1 = 66 MHz. Output enable. 1 = enabled, 0 = disabled (tri-state) Output clock, group 3, 33 or 66 MHz. Output clocks, group 2, 33 or 66 MHz. Output clocks, group 1, 33 or 66 MHz. Output clocks, group 0, 33 or 66 MHz. 3.3V Power supply for outputs CLKG0_(7:6). 3.3V Power supply for outputs CLKG0_(5:3). 3.3V Power supply for outputs CLKG0_(2:0). Ground for output buffers CLKG0_(7:6). Ground for output buffers CLKG0_(5:3). Ground for output buffers CLKG0_(2:0). 3.3V Power supply for outputs CLKG1_(3:2). Ground for output buffers CLKG1_(3:2). 3.3V Power supply for outputs CLKG1_(1:0). Ground for output buffers CLKG1_(1:0). 3.3V Power supply for outputs CLKG2_(1:0). Ground for output buffers. 3.3V Power supply for outputs. Ground for output buffers. Page 2 of 13 Document #: 38-07542 Rev. ** CY28510 Pin Description (continued) Pin 26 25 4 5 8 11 Name VDDA VSSA VDDX VSSX VDDC VSSC Type PWR GND PWR GND PWR GND Power Description 3.3V Power supply for analog PLLs. Ground for analog PLLs. 3.3V Power supply for oscillator. Ground for oscillator. 3.3V Power supply for core. Ground for core. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, yet the interface is available at any time except power-down. Data Protocol The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The Block Write and Block Read protocol is outlined in Table 2, while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address can be D0, D2, D4, or D6 depending on the state of the ADDSEL(0:1) pins. Table 1. Command Code Definition Bit 7 (6:0) 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be ’0000000’ Description Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte count from master – 8 bits Acknowledge from slave Data byte 0 from master– 8 bits Acknowledge from slave Data byte 1 from master – 8 bits Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Block Read Protocol Description Document #: 38-07542 Rev. ** Page 3 of 13 CY28510 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit .... .... .... .... Description Data bytes from master/Acknowledge Data Byte N – 8 bits Acknowledge from slave Stop Bit 39:46 47 48:55 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Not acknowledge Stop Byte Read Protocol Description Block Read Protocol Description Data byte 0 from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data bytes from slave/acknowledge Data byte N from slave – 8 bits Not acknowledge Stop 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Serial Control Registers Byte 0: Clock Enable Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name CLKG0_0 CLKG0_1 CLKG0_2 CLKG0_3 CLKG0_4 CLKG0_5 CLKG0_6 CLKG0_7 Description 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state Page 4 of 13 Document #: 38-07542 Rev. ** CY28510 Byte 1: Clock Enable Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name CLKG1_0 CLKG1_1 CLKG1_2 CLKG1_3 CLKG2_0 CLKG2_1 CLKG3 REF 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state 1 = enabled, 0 = tri-state Description Byte 2: Clock Spread Spectrum Control Register Bit 7 6 5 4 3 @Pup 0 0 0 0 0 SWFSEL CPNTRL1 Charge Pump Control Bit1. See Table 4. Refer to CPNTRL0 in Byte 4, bit 0. CLK output strength, 0 = low, 1 = high. 0=GFS(3:0) controls output frequency. 1 =I 2C selection of output frequency. Output frequencies should be set in Clock Frequency Select Registers before enabling them. Master Spread Spectrum Enable. 1 = enabled, 0 = disabled. SST1 Select spread percentage. See Table 5 SST0 Select spread percentage. See Table 5 Table 5. Spread Spectrum Table [2] PLL Bandwidth 18 to 20 KHz 21 to 23 KHz 24 to 26 KHz 15 to 17 KHz SST1 0 0 1 1 SST0 0 1 0 1 % Spread –0.25% Down spread Lexmark profile –0.50% Down spread Lexmark profile –1.0% Down spread Lexmark profile –1.0% Down spread Linear profile Name Description B2b7, B2b6: 00 = normal, 01 = testb_output, 10 = PD_resetb, 11 = normal 2 1 0 1 0 0 MSTRSRD SST1 SST0 Table 4. Charge Pump Control [1] SST1 0 0 1 1 SST0 0 1 0 1 % Spread 100% 114% 143% 88% Notes: 1. The bandwidth of the non-spread PLL is 80 KHz. 2. Glitch free operation for both enabling and disabling Spread Spectrum Document #: 38-07542 Rev. ** Page 5 of 13 CY28510 . Byte 3: Clock Spread Enable Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CLKG0_0 CLKG0_1 CLKG0_2 CLKG0_3 CLKG0_4 CLKG0_5 CLKG0_6 CLKG0_7 Description Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Byte 4: Clock Spread Enable Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CLKG1_0 CLKG1_1 CLKG1_2 CLKG1_3 CLKG2_0 CLKG2_1 CLKG3 CPNTRL0 Description Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Spread spectrum control. 0 = disabled, 1 = enabled Charge Pump Control Bit1. See Table 4. Refer to CPNTRL1 in Byte 2, bit 5. Byte 5: Clock Frequency Select Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CLKG0_0 CLKG0_1 CLKG0_2 CLKG0_3 CLKG0_4 CLKG0_5 CLKG0_6 CLKG0_7 Description Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Byte 6: Clock Frequency Select Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CLKG1_0 CLKG1_1 CLKG1_2 CLKG1_3 CLKG2_0 CLKG2_1 CLKG3 DAFEN Description Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz Frequency select. 0 = 33 MHz, 1 = 66 MHz M and N register mux selection. 0 = M and N values come from the ROM. 1 = data is loaded from the DAF registers into M and N. Page 6 of 13 Document #: 38-07542 Rev. ** CY28510 Byte 7: Dial-a-Frequency® Control Register N [default = 66.669 MHz, N = 149d, M = 8d] Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 1 0 1 0 1 N7, MSB N6 N5 N4 N3 N2 N1 N0, LSB Description Dial-a-Frequency Operation VCO Frequency = (14.318180 MHz) x (N/ M) Output1 = VCO/4 = 66.669 MHz Output2 = VCO/8 = 33.335 MHz To operate the Dial-a-Frequency feature, you must select the individual output that is to be modified by selecting the Spread spectrum control enable bit in the Clock Spread Enable Registers to multiplex the SS PLL as the input source, which is the only PLL that can have the “N” register value changed. Then you must disable spread spectrum by setting MSTRSRD in the Clock Spread Spectrum Control Register (Byte 2, bit 2) to 0 so that the spread PLL is not being modulated. It is then possible to change the N value from it’s default value of 149 to any value within ±25%. You must also set the DAFEN bit to a 1 in Byte 6, bit 0 to enable the Dial-a-Frequency feature. Please note that the long-term or accumulated jitter will be about 3nsec, which does not affect the operation of the device since only Cycle-to-Cycle jitter can cause system problems. Crystal Recommendations The CY28510 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28510 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. See Table 6. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. Figure 1. Crystal Capacitive Clarification Table 6. Crystal Recommendations Frequency (Fund) 14.31818 MHz Load Cap 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm Cut AT Loading Parallel Document #: 38-07542 Rev. ** Page 7 of 13 CY28510 Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be 2 times the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci1 Ci2 Pin 3 to 6p Cs1 X1 X2 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be 2 times the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) CLe Total Capacitance (as seen by the crystal) = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL CLe Ce Cs Ci Crystal load capacitance Actual loading seen by crystal using standard value trim capacitors External trim capacitors Stray capacitance (trace,etc) Internal capacitance (lead frame, bond wires etc) should have a separate VDD pool and it’s own 0.1 µF capacitor. The more you can avoid external coupling across VDD planes, the better each sub-net can operate at a different frequency, whether jitter is on or off, or it is at a different frequency. Layout and Decoupling Consideration The VDD nets for each of the subgroups within each group are not connected internally. What this implies is that each group Document #: 38-07542 Rev. ** Page 8 of 13 CY28510 VD D _ALL C LK REF 2 .0 V < 1 .2 m s e c Figure 3. Power-up Signal Timing CLK_STOP# Clarification The CLK_STOP# signal is an active low input used for synchronous stopping and starting the CLK output clocks while the rest of the clock generator continues to function. CLK_STOP# Assertion When CLK_STOP# pin is asserted low, all CLK outputs will be stopped after being sampled by two rising CLK internal clock edges. CLK_STOP# CLK CLK Internal Figure 4. CLK_STOP# Assertion Waveforms CLK_STOP# Deassertion The deassertion of the CLK_STOP# signal will cause all CLK outputs that were stopped to resume normal operation in a synchronous manner, synchronous manner meaning that no short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than 2 CLK clock cycles CLK_STOP# CLK CLK Internal Figure 5. CLK_STOP# Deassertion Waveforms Document #: 38-07542 Rev. ** Page 9 of 13 CY28510 Absolute Maximum Conditions Parameter VDD, VDDC, VDDA VDDQ VIN TS TA TJ ØJC ØJA ESDHBM UL–94 MSL Description 3.3V Supply Voltage Output Buffer Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Condition Maximum functional voltage Maximum functional voltage Relative to VSS Non Functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 @1/8 in. 2000 V–0 1 Min. –0.5 –0.5 –0.5 –65 0 Max. 5.5 5.5 VDD + 0.5 150 70 150 15 45 – Unit V V V °C °C °C °C/W °C/W V DC Electrical Specifications Parameter VDD, VDDC, VDDA VDDQ VIL VIH IILC IIL IIH VOL VOH Ioz CIN COUT LIN CXTAL IDD1 IDD2 Description 3.3V Supply Voltage Output Buffer Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Output Low Voltage Output High Voltage Tri-State leakage Current Input pin capacitance Output pin capacitance Input pin Inductance Crystal pin capacitance 3.3V Core Supply Current 3.3V REF Supply Current Measured from the Xin or Xout to VSS All outputs disabled running at the default frequency REF buffer with load from Table 7, running at the default frequency 1 CLK buffer with load from Table 7, running at the default frequency Running at the default frequency Except for internal pull-up or pull-down resistors For internal pull-up resistors For internal pull-down resistors Conditions Maximum operating voltage Maximum operating voltage Min. 3.135 3.135 – 2.0 –5 9 –9 – 2.4 – – – – – – – Typ. 3.3 3.3 – – – – – – – – – – – – 61.80 4.15 Max. 3.465 3.465 0.8 – 5 – – 0.4 – 10 5 6 7 5 – – Unit V V Vdc Vdc µA µA µA Vdc Vdc µA pF pF pF pF mA mA IDD3 3.3V CPU Supply Current – 11.81 – mA IDD4 3.3V VDDA Supply Current – 12 – mA Document #: 38-07542 Rev. ** Page 10 of 13 CY28510 AC Electrical Specifications 66 MHz Parameter CLK FVCO TDC TRISE/TFALL TGSKEW1 TGSKEW2 TCCJ1 Description VCO Frequency Range CLK Duty Cycle CLK Rise and Fall Times Condition Measured at 1.5V Measured at 1.5V Measured from 0.4V to 2.4V Min. 200 45 0.5 – – – Typ. – – – – – – Max. 333 55 3.0 150 150 150 Unit MHz % ns ps ps ps Any CLK to Any CLK Clock Skew Measured at 1.5V, with Spread within a Group Spectrum disabled. Any CLK to Any CLK Clock Skew Measured at 1.5V, with Spread within any Group Spectrum disabled. CLK Cycle-to-Cycle Jitter Measured at 1.5V and all CLKs running the same frequency with Spread Spectrum disabled. Measured at 1.5V and all CLKs running the same frequency with Spread Spectrum enabled Measured at 1.5V with CLKs running different frequencies but the same frequency within a Group and Sub-group and Spread Spectrum disabled Measured at 1.5V with CLKs running different frequencies including within a Sub-group and Spread Spectrum disabled Measured at 1.5V with CLKs running different frequencies including within a Sub-group and Spread Spectrum enabled Measured at 1.5V TCCJ2 CLK Cycle-to-Cycle Jitter – 200 ps TCCJ3 CLK Cycle-to-Cycle Jitter – – 200 ps TCCJ4 CLK Cycle-to-Cycle Jitter – – 400 ps TCCJ5 CLK Cycle-to-Cycle Jitter – – 600 ps SCLK TI2C REF Xin TDC TRISE/TFALL TCCJ TXS I2C Clock Period 1.0 – – us XIN being driven by an external clock source REF Duty Cycle REF Rise and Fall times REF Cycle-to-Cycle Jitter Power-on Hold Off Measured at 1.5V, See Figure 3 Measured from 0.4V to 2.4V, See Figure 3 Measured at 1.5V, See Figure 3 Outputs will be as shown in Figure 3 10 45 1 – – – – – 450 – 18 55 4 1000 1.2 MHz % ns ps ms Table 7. Signal Loading Table Clock Name CLK REF Max Load (pF) 22 15 Document #: 38-07542 Rev. ** Page 11 of 13 CY28510 CLK/REF VDDQ Measurement Point CLOAD 3.3V Figure 6. Output Test Loading Ordering Information Part Number CY28510OC CY28510OCT Package Type 48-pin Shrunk Small Outline package (SSOP) 48-pin Shrunk Small Outline package (SSOP) - Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Package Drawing and Dimension 48-Lead Shrunk Small Outline Package O48 51-85061-C Dial-A-Frequency is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Document #: 38-07542 Rev. ** Page 12 of 13 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.. CY28510 Document History Page Document Title: CY28510 Peripheral I/O Clock Generator Document Number: 38-07542 Rev. ** ECN No. 126023 Issue Date 04/30/03 Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07542 Rev. ** Page 13 of 13