CY29352AXI

CY29352 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications. The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in three banks of five, four, and two outputs. Bank A divides the VCO output by four and six while bank B divides by four and two, and bank C divides by two and four per SEL(A:C) settings, see Table 3 on page 3. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output drives one or two traces, giving the device an effective fanout of 1:22. The PLL is stable if the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 16.67 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO runs at multiples of the input reference clock set by the feedback divider, see Table 2 on page 3. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Output frequency range: 16.67 MHz to 200 MHz Input frequency range: 16.67 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V and 3.3V outputs ±2% maximum output duty cycle variation 11 clock outputs: drive up to 22 clock lines LVCMOS reference clock input 125 ps maximum output-output skew PLL bypass mode Spread Aware™ Output enable and disable Pin compatible with MPC9352 and MPC952 Industrial temperature range: –40°C to +85°C 32-pin 1.4 mm TQFP package Block Diagram PLL_EN# REFCLK FB_IN LPF ÷4 / ÷6 Phase Detector VCO 200-500MHz ÷2 QA0 QA1 QA2 QA3 QA4 VCO_SEL SELA ÷4 / ÷2 QB0 QB1 SELB QB2 QB3 ÷2 / ÷4 QC0 QC1 SELC MR/OE# Cypress Semiconductor Corporation Document Number: 38-07476 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 14, 2008 [+] Feedback CY29352 Pinouts Figure 1. Pin Diagram - 32-pin 1.4 mm TQFP package VDDQC QC1 QC0 VSS VSS QB3 QB2 VDDQB 32 31 30 29 28 27 26 25 VCO_SEL SELC SELB SELA MR/OE# REFCLK AVSS FB_IN 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 CY29352 VSS QB1 QB0 VDDQB VDDQA QA4 QA3 VSS Table 1. Pin Definition - 32-pin 1.4 mm TQFP package Pin 6 22, 23, 26, 27 30, 31 8 Name REFCLK QB(0:3) QC(0,1) FB_IN O O O I, PD IO[1] I, PD Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Reference clock input Clock output bank A Clock output bank B Clock output bank C Feedback clock input. Connect to an output for normal operation. This input must be at the same voltage rail as input reference clock, see Table 2 on page 3. VCO divider select input, see Table 3 on page 3. Master reset or output enable and disable input, see Table 3 on page 3. PLL enable and disable input, see Table 3 on page 3. Frequency select input, bank (A:C), see Table 3 on page 3. 2.5V or 3.3V power supply for bank A output clocks [2,3] 2.5V or 3.3V power supply for bank B output clocks [2,3] 2.5V or 3.3V power supply for bank C output clocks [2,3] 2.5V or 3.3V power supply for PLL [2,3] 2.5V or 3.3V power supply for core and inputs [2,3] Analog ground Common ground Description 12, 14, 15, 18, 19 QA(0:4) 1 5 9 2, 3, 4 16, 20 21, 25 32 10 11 7 VCO_SEL MR/OE# PLL_EN# SEL(A:C) VDDQA VDDQB VDDQC AVDD VDD AVSS I, PD I, PD I, PD I, PD Supply Supply Supply Supply Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground 13, 17, 24, 28, 29 VSS Notes 1. PD = Internal pull down. 2. A 0.1-μF bypass capacitor must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, the high frequency filtering characteristics are cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins. Document Number: 38-07476 Rev. *B PLL_EN# AVDD VDD QA0 VSS QA1 QA2 VDDQA 9 10 11 12 13 14 15 16 Page 2 of 9 [+] Feedback CY29352 Table 2. Frequency Table VCO_SEL 0 0 0 1 1 1 Table 3. Function Table Control VCO_SEL PLL_EN# MR/OE# SELA SELB SELC Default 0 0 0 0 0 0 VCO 0 VCO ÷ 2 1 Feedback Output Divider ÷2 ÷4 ÷6 ÷2 ÷4 ÷6 VCO Input clock * 2 Input clock * 4 Input clock * 6 Input clock * 4 Input clock * 8 Input clock * 12 Input Frequency Range (AVDD = 3.3V) 100 MHz to 200 MHz 50 MHz to 125 MHz 33.33 MHz to 83.33 MHz 50 MHz to 125 MHz 25 MHz to 62.5 MHz 16.67 MHz to 41.67 MHz Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz 50 MHz to 100 MHz 33.33 MHz to 66.67 MHz 50 MHz to 100 MHz 25 MHz to 50 MHz 16.67 MHz to 33.33 MHz PLL enabled, the VCO output connects Bypass mode, PLL disabled, the input clock to the output dividers connects to the output dividers Outputs enabled QA = VCO ÷ 4 QB = VCO ÷ 4 QC = VCO ÷ 2 Outputs disabled (three-state), VCO runs at its minimum frequency QA = VCO ÷ 6 QB = VCO ÷ 2 QC = VCO ÷ 4 Absolute Maximum Conditions Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ ØJC ØJA ESDH FIT Description DC supply voltage DC operating voltage DC input voltage DC output voltage Output termination voltage Latch up immunity Power supply ripple Temperature, storage Temperature, operating ambient Temperature, junction Dissipation, junction to case Dissipation, junction to ambient ESD protection (human body model) Failure in time Manufacturing test Functional Ripple frequency < 100 kHz Non functional Functional Functional Functional Functional 2000 10 –65 –40 200 150 +150 +85 155 42 105 Functional Relative to VSS Relative to VSS Condition Min –0.3 2.375 –0.3 –0.3 Max 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD ÷ 2 Unit V V V V V mA mVp-p °C °C °C °C/W °C/W Volts ppm Document Number: 38-07476 Rev. *B Page 3 of 9 [+] Feedback CY29352 DC Parameters (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input voltage, low Input voltage, high Output voltage, low Input current, low Input current, high [5] [4] Condition LVCMOS LVCMOS IOL = 15 mA IOH = –15 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Min 1.7 1.8 Typ Max 0.7 VDD + 0.3 0.6 –10 100 Unit V V V V μA μA mA mA mA pF Ω Output voltage, high[4] PLL supply current Quiescent supply current Dynamic supply current Input pin capacitance Output impedance 5 3 170 4 17–20 10 5 DC Parameters (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter VIL VIH VOL VOH IIL IIH IDDA VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input voltage, low Input voltage, high Output voltage, low[4] LVCMOS LVCMOS IOL = 24 mA IOL = 12 mA Output voltage, high[4] Input current, low Input current, high[5] PLL supply current Input voltage, low Input voltage, high Output voltage, low[4] IOH = –24 mA VIL = VSS VIL = VDD AVDD only LVCMOS LVCMOS IOL = 24 mA IOL = 12 mA Output voltage, high[4] Input current, low Input current, high[5] PLL supply current Quiescent supply current Dynamic supply current Input pin capacitance Output impedance IOH = –24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD 5 3 240 4 14–17 2.4 –10 100 10 5 2.0 5 2.4 –10 100 10 0.8 VDD + 0.3 0.55 0.30 V μA μA mA mA mA pF Ω 2.0 Condition Min Typ Max 0.8 VDD + 0.3 0.55 0.30 V μA μA mA V V V Unit V V V Notes 4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 5. Inputs have pull down resistors that affect the input current. Document Number: 38-07476 Rev. *B Page 4 of 9 [+] Feedback CY29352 AC Parameters (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter[6] fVCO fin Description VCO frequency Input frequency ÷2 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷12 feedback Bypass mode (PLL_EN# = 1) frefDC tr , tf fMAX Input duty cycle TCLK input rise and fall time Maximum output frequency 0.7V to 1.7V ÷2 output ÷4 output ÷6 output ÷8 output ÷12 output DC tr , tf t(φ) tsk(O) tsk(B) Output duty cycle Output rise and fall times Propagation delay (static phase offset) Output to output skew Bank to bank skew fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V TCLK to FB_IN, same VDD, does not include jitter Skew within bank Banks at same voltage, same frequency Banks at same voltage, different frequency tPLZ, HZ tPZL, ZH BW Output disable time Output enable time PLL closed loop bandwidth (–3 dB) ÷2 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷12 feedback tJIT(CC) tJIT(PER) tJIT(φ) tLOCK Cycle to cycle jitter Period jitter IO phase jitter Maximum PLL lock time Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300 MHz VCO > 300 MHz 150 100 1 ms 2 1–1.5 0.6 0.75 0.5 100 300 100 150 ps ps ps 100 50 33.33 25 16.67 47 44 0.1 -100 Condition Min 200 100 50 33.33 25 16.67 0 25 Typ Max 400 200 100 66.67 50 33.33 200 75 1.0 200 100 66.67 50 33.33 53 56 1.0 100 125 175 225 8 10 ns ns MHz ns ps ps ps % % ns MHz Unit MHz MHz Document Number: 38-07476 Rev. *B Page 5 of 9 [+] Feedback CY29352 AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C) Parameter[6] fVCO fin Description VCO frequency Input frequency ÷2 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷12 feedback Bypass mode (PLL_EN# = 1) frefDC tr , tf fMAX Input duty cycle TCLK input rise and fall time Maximum output frequency 0.8V to 2.0V ÷2 output ÷4 output ÷6 output ÷8 output ÷12 output DC t(φ) tsk(O) tsk(B) Output duty cycle Propagation delay (static phase offset) Output to output skew Bank to bank skew fMAX < 100 MHz TCLK to FB_IN, same VDD, does not include jitter Skew within each Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage tPLZ, HZ tPZL, ZH BW Output disable time Output enable time PLL closed loop bandwidth (–3 dB) ÷2 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷12 feedback tJIT(CC) tJIT(PER) tJIT(φ) tLOCK Cycle to cycle jitter Period jitter IO phase jitter Maximum PLL lock time Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300 MHz VCO > 300 MHz 150 100 1 ms 2 1–1.5 0.6 0.75 0.5 100 275 100 150 ps ps ps 100 50 33.33 25 16.67 48 –100 Condition Min 200 100 50 33.33 25 16.67 0 25 Typ Max 500 200 125 83.33 62.5 41.67 200 75 1.0 200 125 83.33 62.5 41.67 52 200 125 175 235 425 8 10 ns ns MHz % ps ps ps % ns MHz Unit MHz MHz Note 6. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. Document Number: 38-07476 Rev. *B Page 6 of 9 [+] Feedback CY29352 Figure 2. AC Test Reference for VDD = 3.3V / 2.5V P ulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 5 0 ohm R T = 5 0 ohm VTT VTT Figure 3. Propagation Delay t(φ), Static Phase Offset LVCMOS_CLK VDD V DD /2 GND V DD FB_IN V DD /2 t( φ) GND Figure 4. Output Duty Cycle (DC) V DD tP T0 V DD/2 GND DC = tP / T0 x 100% Figure 5. Output to Output Skew, tsk(O) VD D VDD/2 GND VD D VDD/2 tSK(O) GND Document Number: 38-07476 Rev. *B Page 7 of 9 [+] Feedback CY29352 Ordering Information Part Number Pb-Free CY29352 AXI CY29352 AXIT 32-pin TQFP 32-pin TQFP—tape and reel Industrial, –40°C to +85°C Industrial, –40°C to 85°C Package Type Product Flow Package Drawing and Dimension Figure 6. 32 Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm 51-85088-*B Document Number: 38-07476 Rev. *B Page 8 of 9 [+] Feedback CY29352 Document History Page Document Title:CY29352 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Document Number: 38-07476 REV. ** *A *B ECN No. Issue Date 124654 739798 1923227 03/21/03 See ECN See ECN Orig. of Change RGL RGL New Data Sheet Removed the leaded parts and replaced by lead-free parts Description of Change PYG/KVM/ Corrected package thickness from 1.0 mm to 1.4 mm in Features section on AESA page 1 and in Figure 5. © Cypress Semiconductor Corporation, 2003-2008. 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Document Number: 38-07476 Rev. *B Revised January 14, 2008 Page 9 of 9 Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback