CY29940

40 CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features • • • • • • 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 150 ps max. output-to-output skew Dual or single supply operation: — 3.3V core and 3.3V outputs — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin compatible with MPC940L, MPC9109 • Available in Commercial and Industrial temperature • 32-pin LQFP package Description The CY29940 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Block Diagram Pin Configuration VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL 0 1 VDDC 32 31 30 29 28 27 26 25 VSS VSS TCLK TCLK_SEL PECL_CLK PECL_CLK# VDD VDDC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS 18 Q0-Q17 Cypress Semiconductor Corporation Document #: 38-07283 Rev. *B • 3901 North First Street • San Jose Q17 Q16 Q15 VSS Q14 Q13 Q12 VDDC 9 10 11 12 13 14 15 16 Q0 Q1 Q2 VDDC Q3 Q4 Q5 VSS CY29940 • CA 95134 • 408-943-2600 Revised December 21, 2002 CY29940 Pin Description[1] Pin 5 6 3 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 8, 16, 29 7, 21 1, 2, 12, 17, 25 Name PECL_CLK PECL_CLK# TCLK Q(17:0) VDDC PWR I/O I, PU I, PD I, PD O PECL Input Clock PECL Input Clock External Reference/Test Clock Input Clock Outputs Description TCLK_SEL VDDC VDD VSS I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground Note: 1. PD = Internal Pull-Down, PU = Internal Pull-up. Document #: 38-07283 Rev. *B Page 2 of 7 CY29940 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD Protection............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter VIL VIH IIL IIH VPP Description Input Low Voltage Input High Voltage Input Low Current [3] [3] Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD –200 200 Unit. V V µA µA mV Input High Current Peak-to-Peak Input Voltage PECL_CLK Common Mode Range[4] PECL_CLK Output Low Output High Voltage[5, 6, 7] Voltage[5, 6, 7] VDD = 3.3V VDD = 2.5V IOL = 20 mA IOH = –20 mA, VDDC = 3.3V IOH = –20 mA, VDDC = 2.5V 500 1000 VCMR VOL VOH IDDQ IDD VDD – 1.4 VDD – 1.0 2.4 1.8 5 VDD – 0.6 VDD – 0.6 0.5 V V V V V Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 150 MHz, CL=15 pF VDD = 3.3V, Outputs @ 200 MHz, CL=15 pF VDD = 2.5V, Outputs @ 150 MHz, CL=15 pF VDD = 2.5V, Outputs @ 200 MHz, CL=15 pF 7 mA mA 285 335 200 240 8 10 12 15 4 16 20 Zout Cin Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V Ω pF Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines 5. Outputs driving 50Ω transmission lines. 6. See Figure 1 &2. 7. 50% input duty cycle. Document #: 38-07283 Rev. *B Page 3 of 7 CY29940 AC Parameters[8]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter Fmax tPD Description Input Frequency PECL_CLK to Q