CY29948AXIT

CY29948 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer Features • 2.5V or 3.3V operation • 200-MHz clock support • LVPECL or LVCMOS/LVTTL clock input • LVCMOS-/LVTTL-compatible inputs • 12 clock outputs: drive up to 24 clock lines • Synchronous Output Enable • Output three-state control • 150 ps typical output-to-output skew • Pin compatible with MPC948, MPC948L, MPC9448 • Available in Commercial and Industrial temp. range • 32-pin TQFP package Description The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 12 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:24. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The CY29948 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL SYNC_OE TS# 0 1 VDDC Pin Configuration Q0 VDDC Q2 VDDC 27 26 VSS Q1 VSS Q3 25 24 23 22 21 20 19 18 17 32 31 30 12 Q0-Q11 TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 29 28 CY29948 9 10 11 12 13 14 15 16 VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 VSS Q9 Cypress Semiconductor Corporation Document #: 38-07288 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 16, 2006 [+] [+] Feedback VDDC Q10 VDDC Q8 VSS Q11 CY29948 Pin Description[1] Pin 3 4 2 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 1 5 6 10, 14, 18, 22, 26, 30 7 8, 12, 16, 20, 24, 28, 32 Name PECL_CLK PECL_CLK# TCLK Q(11:0) VDDC PWR I/O I, PU I, PD I, PU O PECL Input Clock PECL Input Clock External Reference/Test Clock Input Clock Outputs Description TCLK_SEL SYNC_OE TS# VDDC VDD VSS I, PU I, PU I, PU Clock Select Input. When LOW, PECL clock is selected. When HIGH TCLK is selected. Output Enable Input. When asserted HIGH, the outputs are enabled. When set LOW the outputs are disabled in a LOW state. Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 2.5V or 3.3V Power Supply for Output Clock Buffers 2.5V or 3.3V Power Supply Common Ground Output Enable/Disable The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. TCLK SYNC_OE Q Figure 1. SYNC_OE Timing Diagram Note: 1. PD = Internal pull-down, PU = Internal pull-up. Document #: 38-07288 Rev. *C Page 2 of 8 [+] [+] Feedback CY29948 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection: .............................................. 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range. Parameter VIL Description Input Low Voltage Conditions VDD = 3.3V, PECL_CLK single ended VDD = 2.5V, PECL_CLK single ended All other inputs VIH Input High Voltage VDD = 3.3V, PECL_CLK single ended VDD = 2.5V, PECL_CLK single ended All other inputs IIL IIH VPP VCMR VOL VOH IDDQ IDD Input Low Current[3] Input High Current[3] Peak-to-Peak Input Voltage PECL_CLK Common Mode Range[4] PECL_CLK Output Low Voltage[5] VDD = 3.3V VDD = 2.5V IOL = 20 mA IOH = –20 mA, VDD = 3.3V IOH = –20 mA, VDD = 2.5V Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 100 MHz, CL = 30 pF VDD = 3.3V, Outputs @ 160 MHz, CL = 30 pF VDD = 2.5V, Outputs @ 100 MHz, CL = 30 pF VDD = 2.5V, Outputs @ 160 MHz, CL = 30 pF Zout Cin Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V 2.5 1.8 – – – – – 12 14 – Min. 1.49 1.10 VSS 2.135 1.75 2.0 – – 300 VDD – 2.0 VDD – 1.2 Typ. – – – – – – – – – – – – – – 5 180 270 125 190 15 18 4 Max. 1.825 1.45 0.8 2.42 2.0 VDD –100 100 1000 VDD – 0.6 VDD – 0.6 0.4 – – 7 – – – – 18 22 – pF Ω mA mA V V mV V µA V Unit V Output High Voltage[5] Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07288 Rev. *C Page 3 of 8 [+] [+] Feedback CY29948 AC Parameters[6] VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified operating range. Parameter Fmax Tpd Description Input Frequency[7] PECL_CLK to Q Delay TCLK to Q Delay [7] [7] Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V Measured at VDD/2 Min. Typ. – – Max. 200 170 8.0 8.9 10.0 10.9 55 10 10 250 1.5 2.0 – – – – 1.0 1.3 Unit MHz ns 4.0 4.4 6.0 6.4 45 2 2 – – – – – – – – 150 – – – – – – – – PECL_CLK to Q Delay[7] TCLK to Q Delay[7] FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew(pp) Ts Th Tr/Tf Output Duty Cycle [7, 8, 9] % ns ns ps ns ns ns ns Output Enable Time (all outputs) Output Disable Time (all outputs) Output-to-Output Skew Part-to-Part Skew Set-up Time[7, 10] Hold Time [7, 10] [11] [7, 9] PECL_CLK to Q TCLK to Q SYNC_OE to PECL_CLK SYNC_OE to TCLK PECL_CLK to SYNC_OE TCLK to SYNC_OE 0.8V to 2.0V, VDD = 3.3V 0.6V to 1.8V, VDD = 2.5V – – 1.0 0.0 0.0 1.0 0.20 0.20 Output Clocks Rise/Fall Time[9] CY29948 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 5 0 ohm R T = 5 0 ohm VTT VTT Figure 2. LVCMOS_CLK CY29948 Test Reference for VCC = 3.3V and VCC = 2.5V Zo = 50 ohm Differential Pulse Generator Z = 50 ohm CY29948 DUT Zo = 50 ohm Zo = 50 ohm R T = 5 0 ohm R T = 5 0 ohm VTT VTT Figure 3. PECL_CLK CY29948 Test Reference for VCC = 3.3V and VCC = 2.5V Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. See Figures 2 and 3. 10. Setup and hold times are relative to the falling edge of the input clock 11. Part-to-Part skew at a given temperature and voltage. Document #: 38-07288 Rev. *C Page 4 of 8 [+] Feedback CY29948 PEC L_C LK PEC L_C LK VPP V CMR VCC Q V C C /2 t PD GND Figure 4. Propagation Delay (TPD) Test Reference LVCMOS_CLK VCC VCC /2 GND VCC Q VCC /2 t PD GND Figure 5. LVCMOS Propagation Delay (TPD) Test Reference VCC VCC /2 tP T0 DC = tP / T0 x 100% GND Figure 6. Output Duty Cycle (FoutDC) VCC VCC /2 GND VCC VCC /2 GND t SK(0) Figure 7. Output-to-Output Skew tsk(0) Document #: 38-07288 Rev. *C Page 5 of 8 [+] [+] Feedback CY29948 Ordering Information Part Number CY29948AI CY29948AIT CY29948AC CY29948ACT Lead-free CY29948AXI CY29948AXIT CY29948AXC CY29948AXCT 32 Pin TQFP 32 Pin TQFP - Tape and Reel 32 Pin TQFP 32 Pin TQFP - Tape and Reel Industrial, -40°C to +85°C Industrial, -40°C to +85°C Commercial, 0°C to +70°C Commercial, 0°C to +70°C Package Type 32 Pin TQFP 32 Pin TQFP - Tape and Reel 32 Pin TQFP 32 Pin TQFP - Tape and Reel Production Flow Industrial, -40°C to +85°C Industrial, -40°C to +85°C Commercial, 0°C to +70°C Commercial, 0°C to +70°C Document #: 38-07288 Rev. *C Page 6 of 8 [+] [+] Feedback CY29948 Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-B All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-07288 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY29948 Revision History Document Title: CY29948 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer Document Number: 38-07288 REV. ** *A *B *C ECN NO. 111099 116782 122880 428221 Issue Date 02/13/02 08/14/02 12/22/02 See ECN Orig. of Change BRK HWT RBI RGL Description of Change New datasheet Added Commercial Temperature Range Added power up requirements to Maximum Ratings Added Lead-free devices Document #: 38-07288 Rev. *C Page 8 of 8 [+] [+] Feedback