CY29976

CY29976 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ Output frequency up to 125 MHz Supports PowerPC , and Pentium processors 12 clock outputs: frequency configurable Configurable Output Disable Two reference clock inputs for dynamic toggling Oscillator or PECL reference input ® ® ■ ■ ■ ■ ■ ■ Spread spectrum compatible Glitch-free output clocks transitioning 3.3V power supply Pin compatible with SC973X Industrial temperature range: –40°C to +85°C 52-Pin TQFP package Table 1. Frequency Table[1] VC0_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FB_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FVCO 8x 12x 16x 20x 8x 12x 16x 20x 4x 6x 8x 10x 4x 6x 8x 10x Note 1. x = the reference input frequency, 200MHz < FVCO < 480MHz. Cypress Semiconductor Corporation Document #: 38-07413 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 09, 2008 [+] Feedback CY29976 Logic Block Diagram PECL PECL_ VCO PL REF _CLK C LK# _SEL L_EN _SEL D TCLK0 TCLK1 TCLK_SEL F B _ IN D Q S ync F rz 0 1 P hase D e te c to r LPF VCO 0 1 Q S ync F rz QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 M R # /O E P o w e r-O n R eset S E L A (0 ,1 ) S E L B (0 ,1 ) S E L C (0 ,1 ) F B _ S E L (0 :2 ) SCLK SDATA IN V _ C L K O u tp u t D is a b le C ir c u itr y 12 2 2 2 3 /4 , /6 , /8 , /1 0 S y n c P u ls e D a ta G e n e ra to r D Q D Q D /2 , /6 , /4 , /1 2 /2 , /6 , /4 , /1 0 /8 , /2 , /6 , /4 D Q Q S ync F rz QC0 QC1 S ync F rz S ync F rz S ync F rz QC2 QC3 FB_O UT SYNC Pinouts VCO_SEL SELA0 SELA1 SELB0 SELB1 VDDC VDDC QA0 QA1 QA2 QA3 VSS VSS 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 CY29976 14 15 16 17 18 19 20 21 22 23 24 25 26 INV_CLK VSS QC3 VDDC QC2 SELC1 SELC0 QC1 VDDC QC0 VSS SYNC FB_SEL1 Document #: 38-07413 Rev. *B Page 2 of 9 [+] Feedback CY29976 Pin Definitions[2] Pin No. 11 12 9 10 44, 46, 48, 50 32, 34, 36, 38 16, 18, 21, 23 29 Pin Name PECL_CLK PECL_CLK# TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT VDDC VDDC VDDC VDDC PWR IO I I I I O O O O Type PU PD PU PU PECL Clock Input. PECL Clock Input. External Reference/Test Clock Input. External Reference/Test Clock Input. Clock Outputs. See Table 2 on page 4 for frequency selections. Clock Outputs. See Table 2 on page 4 for frequency selections. Clock Outputs. See Table 2 on page 4 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1. A bypass delay capacitor at this output controls Input Reference/ Output Banks phase relationships. Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. PU PU PU PU PU PU PU PU PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2 on page 4. Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2 on page 4. Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2 on page 4. Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1 on page 1. VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1 on page 1. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL is bypassed. Reference Select Input. When HIGH, the PECL clock is selected. When LOW, TCLK (0,1) is the reference clock. TCLK Select Input. When LOW, TCLK0 is selected and when HIGH TCLK1 is selected. Master Reset/Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL Common Ground Description 25 SYNC VDDC O 42, 43 40, 41 19, 20 5, 26, 27 52 31 6 7 8 SELA(1,0) SELB(1,0) SELC(1,0) FB_SEL(2:0) VCO_SEL FB_IN PLL_EN REF_SEL TCLK_SEL I I I I I I I I I 2 MR#/OE I PU 14 3 4 17, 22, 28, 33,37, 45, 49 13 1, 15, 24, 30, 35, 39, 47, 51 INV_CLK SCLK SDATA VDDC VDD VSS I I I PU PU PU Note 2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power (