CY62126EV30LL-45ZSXA

CY62126EV30 MoBL 1-Mbit (64K x 16) Static RAM Features ■ High speed: 45 ns ■ Temperature ranges ❐ Industrial: –40 °C to +85 °C ❐ Automotive: –40 °C to +125 °C ■ Wide voltage range: 2.2 V to 3.6 V ■ Pin compatible with CY62126DV30 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 4 A advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life(MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 48-ball very fine pitch ball grid array (VFBGA) and 44-pin thin small outline package (TSOP) II packages Functional Description To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. The CY62126EV30 is a high performance CMOS static RAM organized as 64K words by 16 bits. This device features Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 64K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 • BHE WE CE OE BLE A15 A14 A13 A11 Cypress Semiconductor Corporation Document #: 38-05486 Rev. *H A12 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 17, 2010 CY62126EV30 MoBL Contents Pin Configuration ............................................................. 3 Maximum Ratings............................................................. 4 Operating Range............................................................... 4 Electrical Characteristics................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance.......................................................... 5 Data Retention Characteristics ....................................... 6 Switching Characteristics................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document #: 38-05486 Rev. *H Ordering Information...................................................... Ordering Code Definitions ......................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 12 12 13 14 15 16 16 16 16 Page 2 of 16 CY62126EV30 MoBL Pin Configuration Figure 2. 44-Pin TSOP II (Top View) [1] Figure 1. 48-Ball VFBGA (Top View) 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 Vcc D VCC I/O12 NC NC I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Table 1. Product Portfolio Power Dissipation Product CY62126EV30LL VCC Range (V) Range Industrial CY62126EV30LL Automotive Speed (ns) Min Typ[2] Max 2.2 3.0 3.6 2.2 3.0 3.6 Operating, ICC (mA) f = 1 MHz f = fmax Standby, ISB2 (A) Typ[2] Max Typ[2] Max Typ[2] Max 45 1.3 2 11 16 1 4 55 1.3 4 11 35 1 30 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05486 Rev. *H Page 3 of 16 CY62126EV30 MoBL DC input voltage[3, 4]  0.3 V to 3.6 V (VCCmax + 0.3 V) Maximum Ratings Exceeding maximum ratings may shorten the battery life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage to ground potential .............................. –0.3 V to 3.6 V (VCCmax + 0.3 V) DC voltage applied to outputs in High Z state[3, 4] .............. –0.3 V to 3.6 V (VCCmax + 0.3 V) Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) Latch up current..................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC[5] CY62126EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V Automotive –40 °C to +125 °C Electrical Characteristics (Over the Operating Range) Parameter Description Test Conditions 45 ns (Industrial) 55 ns (Automotive) Min Typ[6] Max Min Typ[6] Max – – 2.0 – – – VOH Output high voltage IOH = –0.1 mA 2.0 IOH = –1.0 mA, VCC > 2.70V 2.4 – – 2.4 VOL Output low voltage IOL = 0.1 mA – – 0.4 – IOL = 2.1mA, VCC > 2.70V – – 0.4 – 1.8 – VCC + 0.3 Unit V – V 0.4 V – 0.4 V 1.8 – VCC + 0.3 V VIH Input high voltage VCC = 2.2 V to 2.7 V VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 2.2 – VCC + 0.3 V VIL Input low voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V VCC = 2.7 V to 3.6 V –0.3 – 0.8 –0.3 – 0.8 V –1 – +1 –4 – +4 A IIX Input leakage current GND < VI < VCC IOZ Output leakage current GND < VO < VCC, Output Disabled ICC VCC operating supply current f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels – +1 –4 – +4 A 11 16 – 11 35 mA – 1.3 2.0 – 1.3 4.0 –1 ISB1 Automatic CE power CE > VCC 0.2 V, down current —CMOS VIN > VCC – 0.2 V, VIN < 0.2 V) inputs f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60V – 1 4 – 1 35 A ISB2 [7] Automatic CE power CE > VCC – 0.2 V, down current —CMOS VIN > VCC – 0.2 V or VIN < 0.2 V, inputs f = 0, VCC = 3.60V – 1 4 – 1 30 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05486 Rev. *H Page 4 of 16 CY62126EV30 MoBL Capacitance For all packages. Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) JC Test Conditions Still Air, soldered on a 4.25 × 1.125 inch, two-layer printed circuit board VFBGA Package 58.85 TSOP II Package 28.2 °C/W 17.01 3.4 °C/W Unit Figure 3. AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF INCLUDING JIG AND SCOPE 10% GND Rise Time = 1 V/ns R2 ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.2 V - 2.7 V 2.7 V - 3.6 V Unit R1 16600 1103  R2 15400 1554  RTH 8000 645  VTH 1.2 1.75 V Document #: 38-05486 Rev. *H Page 5 of 16 CY62126EV30 MoBL Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR[9] Data retention current tCDR [10] tR[10] Conditions Min Typ[8] Max Unit 1.5 – – V Industrial – – 3 A Automotive – – 30 A Chip deselect to data retention time 0 – – ns Operation recovery time tRC – – ns VCC= VDR, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Figure 4. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Tested initially and after any design or process changes that may affect these parameters. 10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s. Document #: 38-05486 Rev. *H Page 6 of 16 CY62126EV30 MoBL Switching Characteristics Over the Operating Range [11, 12] Parameter 45 ns (Industrial) Description 55 ns (Automotive) Min Max Min Max Unit Read Cycle tRC Read cycle time 45 – 55 – ns tAA Address to data valid – 45 – 55 ns tOHA Data hold from address change 10 – 10 – ns tACE CE LOW to data valid – 45 – 55 ns tDOE OE LOW to data valid – 22 – 25 ns [13] 5 – 5 – ns – 18 – 20 ns ns OE LOW to Low Z tLZOE OE HIGH to High Z tHZOE [13, 14] [13] tLZCE CE LOW to Low Z 10 – 10 – tHZCE CE HIGH to High Z [13, 14] – 18 – 20 ns tPU CE LOW to power up 0 – 0 – ns tPD CE HIGH to power down – 45 – 55 ns tDBE BHE / BLE LOW to data valid – 22 – 25 ns tLZBE BHE / BLE LOW to Low Z [13] 5 – 5 – ns – 18 – 20 ns BHE / BLE HIGH to High Z tHZBE Write Cycle [13, 14] [15] tWC Write cycle time 45 – 55 – ns tSCE CE LOW to write end 35 – 40 – ns tAW Address setup to write end 35 – 40 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35 – 40 – ns tBW BHE / BLE pulse width 35 – 40 – ns tSD Data setup to write end 25 – 25 – ns tHD Data hold from write end 0 – 0 – ns – 18 – 20 ns 10 – 10 – ns tHZWE tLZWE WE LOW to High Z [13, 14] WE HIGH to Low Z [13] Notes 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write. Document #: 38-05486 Rev. *H Page 7 of 16 CY62126EV30 MoBL Switching Waveforms Figure 5. Read Cycle No. 1(Address transition controlled)[16, 17] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE controlled)[17, 18] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGHIMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Notes 16. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 17. WE is high for read cycle. 18. Address valid before or similar to CE and BHE, BLE transition LOW. Document #: 38-05486 Rev. *H Page 8 of 16 CY62126EV30 MoBL Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE controlled)[19, 20, 21] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD NOTE 22 tHD DATAIN tHZOE Figure 8. Write Cycle No. 2 (CE controlled)[19, 20, 21] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 22 tHZOE Notes 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write. 20. Data I/O is high impedance if OE = VIH. 21. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 22. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05486 Rev. *H Page 9 of 16 CY62126EV30 MoBL Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [23] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA I/O NOTE 24 tHD DATAIN tLZWE tHZWE Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[23] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 24 tSD tHD DATAIN tLZWE Note 23. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 24. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05486 Rev. *H Page 10 of 16 CY62126EV30 MoBL Truth Table CE[25] WE OE BHE BLE H X X X X Inputs/Outputs Mode Power High Z Deselect/power down Standby (ISB) L X X H H High Z Output disabled Active (ICC) L H L L L Data out (I/O0–I/O15) Read Active (ICC) L H L H L Data out (I/O0–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output disabled Active (ICC) L H H H L High Z Output disabled Active (ICC) L H H L H High Z Output disabled Active (ICC) L L X L L Data in (I/O0–I/O15) Write Active (ICC) L L X H L Data in (I/O0–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data in (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Note 25. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted. Document #: 38-05486 Rev. *H Page 11 of 16 CY62126EV30 MoBL Ordering Information Speed (ns) 45 55 Ordering Code Package Diagram Package Type Operating Range CY62126EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial CY62126EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial CY62126EV30LL-45ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A CY62126EV30LL-55BVXE 51-85150 48-ball VFBGA (Pb-free) Automotive-E CY62126EV30LL-55ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive-E Contact your local Cypress sales representative for availability of other parts. Ordering Code Definitions CY 621 2 6 E V30 LL 45/55 XXX X Temperature Grades: I = Industrial A = Auto-A E = Auto-E Package type: BVX: VFBGA (Pb-free) ZSX: TSOP II (Pb-free) Speed grade Low Power Voltage Range = 3 V Typical E = Process Technology 90 nm Bus Width = x16 Density = 1 Mbit 621 = MoBL SRAM Family Company ID: CY = Cypress Document #: 38-05486 Rev. *H Page 12 of 16 CY62126EV30 MoBL Package Diagrams Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150 *F Document #: 38-05486 Rev. *H Page 13 of 16 CY62126EV30 MoBL Figure 12. 44-Pin TSOP II, 51-85087 11.938 (0.470) 11.735 (0.462) 10.262 (0.404) 10.058 (0.396) PIN 1 I.D. 1 22 Z Z Z Z X Z AA 44 23 BOTTOM VIEW TOP VIEW 0.800 BSC (0.0315) 0.400(0.016) 0.300 (0.012) EJECTOR MARK (OPTIONAL) CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG BASE PLANE 10.262 (0.404) 10.058 (0.396) 0.10 (.004) 18.517 (0.729) 18.313 (0.721) 0.210 (0.0083) 0.120 (0.0047) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) 0°-5° SEATING PLANE 0.597 (0.0235) 0.406 (0.0160) DIMENSION IN MM (INCH) MAX MIN. 51-85087-*C Acronyms Acronym Description BHE byte high enable BLE byte low enable CMOS complementary metal oxide semiconductor CE chip enable I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package VFBGA very fine ball gird array WE write enable Document #: 38-05486 Rev. *H Page 14 of 16 CY62126EV30 MoBL Document History Page Document Title: CY62126EV30 MoBL®, 1-Mbit (64K x 16) Static RAM Document Number: 38-05486 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 202760 See ECN AJU New data sheet *A 300835 See ECN SYT Converted from Advance Information to Preliminary Specified Typical standby power in the Features Section Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package and removed the footnote associated with it on page #2 Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and 45-ns speed bins, respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed bins, respectively Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed bins, respectively Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respectively Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE” on page # 4 Removed footnote that read “If both BHE and BLE are toggled together, then tLZBE is 10 ns” on page # 5 Added Pb-free package information *B 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62126EV30 Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz, ISB1, ISB2 (max) from 1 A to 4 A, ISB1, ISB2 (Typ) from 0.5 A to 1 A, ICCDR (max) from 1.5 A to 3 A, AC Test load Capacitance value from 50 pF to 30 pF, tLZOE from 3 to 5 ns, tLZCE from 6 to 10 ns, tHZCE from 22 to 18 ns, tLZBE from 6 to 5 ns, tPWE from 30 to 35 ns, tSD from 22 to 25 ns, tLZWE from 6 to 10 ns, and updated the Ordering Information table. *C 925501 See ECN VKN Added footnote #7 related to ISB2 and ICCDR Added footnote #11 related AC timing parameters *D 1045260 See ECN VKN Added Automotive information Updated Ordering Information table *E 2631771 01/07/09 NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode Updated template *F 2944332 06/04/2010 VKN Added Contents Removed byte enable from footnote #2 in Electrical Characteristics Added footnote related to chip enable in Truth Table Updated Package Diagrams Updated links in Sales, Solutions, and Legal Information *G 2996166 07/29/2010 AJU Added CY62126EV30LL-45ZSXA part in Ordering Information. Added Ordering Code Definitions. Modified table footnote format. *H 3113864 12/17/2010 PRAS Updated Figure 1 and Package Diagram, and fixed Typo in Figure 3.. Document #: 38-05486 Rev. *H Page 15 of 16 CY62126EV30 MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2010. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05486 Rev. *H Revised December 17, 2010 Page 16 of 16 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.