CY62127DV18_05

PRELIMINARY CY62127DV18 MoBL2® 1 Mb (64K x 16) Static RAM Features • Very high speed: 55 ns • Voltage range: 1.65V to 2.2V • Ultra-low active power — Typical active current: 0.5 mA @ f = 1 MHz — Typical active current: 3.75 mA @ f = fMAX • Ultra-low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • Packages offered in a 48-ball FBGA and a 44-lead TSOP Type II power consumption by 99% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable (CE) HIGH or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable (CE) HIGH, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable (CE) LOW and Write Enable (WE) LOW). Writing to the device is accomplished by taking Chip Enable (CE) LOW and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/Os pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the ad Reading from the device is accomplished by taking Chip Enable (CE) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of re Functional Description[1] The CY62127DV18 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 64K x 16 RAM Array 2048 X 512 SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE CE BHE BLE A11 A12 A13 Power - Down Circuit Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. A14 A15 Cypress Semiconductor Corporation Document #: 38-05226 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 5, 2005 PRELIMINARY Pin Configuration[2] FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 2 OE BHE I/O10 3 A0 A3 A5 4 A1 A4 A6 A7 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 DNU I/O0 I/O2 VCC VSS I/O6 I/O7 DNU A B C D E F G H CY62127DV18 MoBL2® TSOP II (Forward) Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O11 DNU I/O12 DNU DNU I/O13 A14 A12 A9 A15 A13 A10 I/O15 DNU DNU A8 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Note: 2. E3 (DNU) can be left as NC or Vss to ensure proper operation. or left open(Expansion Pins E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M)., NC Pins are not connected to the die. Document #:38-05226 Rev.*A Page 2 of 11 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential .−0.2V to VCCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State[3] .................................... −0.2V to VCC + 0.2V CY62127DV18 MoBL2® DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Range Ambient Temperature (TA) VCC Industrial −40°C to +85°C 1.65V to 2.2V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range(V) Product CY62127DV18L CY62127DV18LL Min. 1.65 Typ. 1.8 Max. 2.2 Speed (ns) 55 55 f = 1 MHz Typ.[4] 0.5 0.5 Max. 1.5 1.5 f = fMAX Typ.[4] 3.75 3.75 Max. 7.5 7.5 Standby, ISB2 (µA) Typ.[4] 0.5 0.5 Max. 5 4 DC Electrical Characteristics Over the Operating Range CY62127DV18-55 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND < VI < VCC GND < VO < VCC, Output Disabled Vcc = 2.2V, IOUT = 0mA, CMOS level L LL L LL Test Conditions IOH = −0.1 mA IOL = 0.1 mA 1.4 −0.2 −1 −1 3.75 0.5 0.5 0.5 0.5 0.5 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 7.5 1.5 5 4 5 4 µA µA Typ.[4] Max. Unit V V V V µA µA mA VCC Operating Supply Cur- f = fMAX = 1/tRC rent f = 1 MHz Automatic CE Power-down Current − CMOS Inputs CE > VCC − 0.2V, VIN > VCC − 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC=2.2V ISB2 Automatic CE Power-down Current − CMOS Inputs Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF Thermal Resistance Parameter θJA Description Test Conditions FBGA 55 TSOP II 76 Unit °C/W °C/W Thermal Resistance (Junction to Ambient)[5] Still Air, soldered on a 3 x 4.5 inch, Thermal Resistance (Junction to Case)[5] two-layer printed circuit board θJC 12 11 Notes: 3. VIL(min.) = −1.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.5V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 5. Tested initially and after any design or proces changes that may affect these parameters. Document #:38-05226 Rev.*A Page 3 of 11 PRELIMINARY AC Test Loads and Waveforms R1 VCC OUTPUT CL = 50 pF INCLUDING JIG AND SCOPE Equivalent to: RTH OUTPUT VTH R2 CY62127DV18 MoBL2® ALL INPUT PULSES VCC Typ 10% GND Rise Time: 1 V/ns 90% 90% 10% Fall Time: 1 V/ns TH VENIN EQUIVALENT É Parameters R1 R2 R TH V TH 1.8V 13500 10800 6000 0.80 UNIT Ω Ω Ω V Data Retention Characteristics Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC=1.5V, CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V L LL 0 100 Conditions Min. 1 Typ.[4] Max. 2.2 4 3 ns µs Unit V µA Data Retention Waveform[7] V VCC CC(min.) DATA RETENTION MODE VDR > 1.5V V CC(min.) tCDR CE tR Notes: 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs. . 7. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both Document #:38-05226 Rev.*A Page 4 of 11 PRELIMINARY Switching Characteristics (Over the Operating Range)[8] CY62127DV18 MoBL2® CY62127DV18-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[10] tHZBE Write Cycle[12] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Read Cycle Time Address to Data Valid Description Min. 55 Max. Unit ns 55 10 55 25 5 20 10 20 0 55 55 5 20 55 40 40 0 0 40 40 25 0 20 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [9] OE HIGH to High Z[9,11] CE LOW to Low Z[9] CE HIGH to High Z[9,11] CE LOW to Power-up CE HIGH to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[9] BLE/BHE HIGH to High-Z[9,11] Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[9,11] WE HIGH to Low Z [9] Notes: 8. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 50 pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t 10. If both byte enables are toggled together, this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signal Document #:38-05226 Rev.*A Page 5 of 11 PRELIMINARY Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13,14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID CY62127DV18 MoBL2® DATA VALID Read Cycle No. 2 (OE Controlled)[14,15] ADDRESS tRC CE tACE OE BHE, BLE tDBE tLZBE tDOE tLZOE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD 50% ISB ICC tHZBE tHZOE tHZCE HIGH IMPEDANCE Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #:38-05226 Rev.*A Page 6 of 11 PRELIMINARY Write Cycle No. 1 (WE Controlled) [11,12, 16, 17, 18] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA CY62127DV18 MoBL2® BHE/BLE tBW OE tSD DATA I/O DON'T CARE tHD DATAIN VALID tHZOE Write Cycle No. 2 (CE Controlled) [11,12, 16, 17, 18] tWC ADDRESS tSCE CE tSA tAW tPWE tHA WE BHE / BLE tBW OE tSD DATA I/O DON'T CARE tHD DATA IN VALID tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #:38-05226 Rev.*A Page 7 of 11 PRELIMINARY Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18] tWC ADDRESS tSCE CE CY62127DV18 MoBL2® BHE /BLE tAW tSA WE tBW tHA tPWE tSD DATA I/O DON'T CARE tHD DATAIN VALID tHZWE tLZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17, 18] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA WE tPWE tSD tHD DATA I/O DON'T CARE DATAIN VALID Document #:38-05226 Rev.*A Page 8 of 11 PRELIMINARY Truth Table X L L L L L L L L L X H H H H H H L L L X L L L H H H X X X H L H L L H L L H L H L L H L L H L L H High Z Data Out Data Out High Z High Z High Z High Z Data In Data In High Z High Z Data Out High Z Data Out High Z High Z High Z Data In High Z Data In Deselect/Power-down Read All bits Read Lower Byte Only Read Upper Byte Only Output Disabled Output Disabled Output Disabled Write Write Lower Byte Only Write Upper Byte Only CY62127DV18 MoBL2® Standby (I SB ) Active (I CC ) Active (I CC ) Active (I CC ) Active (I CC ) Active (I CC ) Active (I CC ) Active (I CC ) Active (I CC ) Active (I CC ) Ordering Information Speed (ns) 55 Ordering Code CY62127DV18L-55BVI CY62127DV18LL-55BVI CY62127DV18L-55ZI CY62127DV18LL-55ZI Package Name BV48A BV48A Z44 Z44 Package Type 48-ball Fine Pitch BGA (6mm x 8mm x 1mm) 48-ball Fine Pitch BGA (6mm x 8mm x 1mm) 44-Lead TSOP Type II 44-Lead TSOP Type II Operating Range Industrial Package Diagrams 48-Ball (6 mm x 8 mm x 1 mm) Fine Pitch BGA BV48A 51-85150-*B Document #:38-05226 Rev.*A Page 9 of 11 PRELIMINARY CY62127DV18 MoBL2® Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05226 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page Document Title: CY62127DV18 MoBL2® 1 Mb (64K x 16) Static RAM Document Number: 38-05226 REV. ** *A ECN NO. Issue Date 118006 127312 10/01/02 06/17/03 Orig. of Change CDY MPR New Data Sheet CY62127DV18 MoBL2® Description of Change Changed status from Advance Information to Preliminary Changed Isb2 to 5 uA(L), 4 uA(LL) Changed Iccdr to 4 uA(L), 3 uA(LL) Changed Cin from 6 pF to 8 pF Document #:38-05226 Rev.*A Page 11 of 11