CY62127DV30 MoBL®
1-Mbit (64K × 16) Static RAM
1-Mbit (64K × 16) Static RAM
Features
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption by 90% when addresses are not toggling. The
device can be put into standby mode reducing power
consumption by more than 99% when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
byte high enable and byte low enable are disabled (BHE, BLE
HIGH) or during a write operation (CE LOW and WE LOW).
■
Temperature ranges
❐ Industrial: –40 °C to 85 °C
■
Very high speed: 55 ns
■
Wide voltage range: 2.2 V to 3.6 V
■
Pin compatible with CY62127BV
■
Ultra-low active power
❐ Typical active current: 0.85 mA at f = 1 MHz
❐ Typical active current: 5 mA at f = fMAX
■
Ultra-low standby power
■
Easy memory expansion with CE and OE features
■
Automatic power-down when deselected
■
Available in Pb-free 48-ball FBGA and 44-pin TSOP Type II
packages
Functional Description
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16-bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
Writing to the device is accomplished by taking chip enable (CE)
and write enable (WE) inputs LOW. If byte low enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A15). If
byte high enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking chip enable
(CE) and output enable (OE) LOW while forcing the write enable
(WE) HIGH. If byte low enable (BLE) is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If byte high enable (BHE) is LOW, then data from memory
appear on I/O8 to I/O15. See the truth table at the back of this
datasheet for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
64K x 16
RAM Array
2048 x 512
SENSE AMPS
ROW DECODER
10
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
A12
A13
A14
A15
A11
COLUMN DECODER
Power -Down
Circuit
CE
BHE
BLE
.
Cypress Semiconductor Corporation
Document Number: 38-05229 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 21, 2017
CY62127DV30 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 38-05229 Rev. *R
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC®Solutions ....................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62127DV30 MoBL®
Product Portfolio
Power Dissipation
Product
CY62127DV30LL
VCC Range (V)
Min
2.2
Typ
3.0
Speed
(ns)
Max
3.6
Operating, ICC (mA)
55
f = 1 MHz
Standby ISB2 (A)
f = fMAX
Typ[1]
Max
Typ[1]
Max
Range
Typ[1]
Max
0.85
1.5
5
10
Industrial
1.5
4
Pin Configurations
Figure 1. 48-ball FBGA pinout [2, 3]
FBGA (Top View)
4
5
3
6
A1
A2
NC
A
A3
A4
CE
I/O0
B
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12 DNU
NC
I/O4
VSS
E
1
2
BLE
OE
A0
I/O8
BHE
I/O9
I/O14 I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Figure 2. 44-pin TSOP Type II pinout [2, 3]
TSOP II (Forward)
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
DNU
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected to the die. Expansion pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M
3. Pin #23 of TSOP-II and E3 ball of FBGA are DNU, which have to be left floating or tied to Vss to ensure proper application.
Document Number: 38-05229 Rev. *R
Page 3 of 17
CY62127DV30 MoBL®
DC input voltage[4] .............................. 0.3 V to VCC + 0.3 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage to ground potential ................0.3 V to 3.9 V
DC voltage applied to outputs
in high Z State[4] ................................. 0.3 V to VCC + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature (TA)
VCC[5]
Industrial
–40 °C to +85 °C
2.2 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output HIGH voltage
Test Conditions
-55
Min
Typ[6]
Max
2.2 VCC 2.7
IOH = 0.1 mA
2.0
–
–
2.7 VCC 3.6
IOH = 1.0 mA
2.4
–
–
–
–
0.4
VOL
Output LOW voltage
2.2 VCC 2.7
IOL = 0.1 mA
2.7 VCC 3.6
IOL = 2.1 mA
–
–
0.4
VIH
Input HIGH voltage
2.2 VCC 2.7
1.8
–
VCC + 0.3
2.7 VCC 3.6
2.2
–
VCC + 0.3
–
0.6
Unit
V
V
V
VIL
Input LOW voltage
2.2 VCC 2.7
0.3
2.7 VCC 3.6
0.3
–
0.8
IIX
Input leakage current
GND VI VCC
1
–
+1
µA
IOZ
Output leakage current
GND VO VCC, Output disabled
1
–
+1
µA
ICC
VCC operating supply current
f = fMAX = 1/tRC
–
5
10
mA
–
0.85
1.5
–
1.5
4
µA
–
1.5
4
µA
f = 1 MHz
ISB1
Automatic CE power-down
current – CMOS Inputs
VCC = 3.6 V,
IOUT = 0 mA,
CMOS level
CE VCC 0.2 V,
V
VIN VCC 0.2 V, VIN 0.2 V,
f = fMAX (Address and data only),
f = 0 (OE, WE, BHE and BLE)
ISB2
Automatic CE power-down
current – CMOS Inputs
CE VCC 0.2 V,
VIN VCC 0.2 V or VIN 0.2 V,
f = 0, VCC = 3.6 V
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns., VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full device operation requires linear ramp of VCC from 0 V to VCC(min) and VCC must be stable at VCC(min) for 500µs.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05229 Rev. *R
Page 4 of 17
CY62127DV30 MoBL®
Capacitance
Parameter [7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
8
pF
8
pF
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [8]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
FBGA
TSOP-II
Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
52.02
62.01
°C/W
10.98
22.08
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
50 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V (2.2 V–2.7 V)
3.0 V (2.7 V–3.6 V)
Unit
R1
16600
1103
R2
15400
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05229 Rev. *R
Page 5 of 17
CY62127DV30 MoBL®
Data Retention Characteristics
Parameter
Description
Conditions
Min
Typ[9]
Max
Unit
1.5
–
–
V
–
3
A
VDR
VCC for data retention
ICCDR
Data retention current
tCDR
Chip deselect to data retention
time
0
–
–
ns
tR[10]
Operation recovery time
55
–
–
ns
VCC = 1.5 V, CE VCC 0.2 V,
VIN VCC 0.2 V or VIN 0.2 V
Data Retention Waveform
Figure 4. Data Retention Waveform [11]
VCC
VCC
CE
oror
CE
. .
BHE
BLE
BHEBLE
VV
CC(min.)
CC(min.)
tCDR
tCDR
DATA
MODE
DATA RETENTION
RETENTION MODE
VDR
> 1.5V
1.5V
DR >
V
VVCC(min.)
CC(min.)
tRtR
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 200 µs.
Document Number: 38-05229 Rev. *R
Page 6 of 17
CY62127DV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [12]
Description
CY62127DV30-55
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
[13]
5
–
ns
Z[13, 14]
–
20
ns
tLZOE
OE LOW to low Z
tHZOE
OE HIGH to high
Z[13]
tLZCE
CE LOW to low
10
–
ns
tHZCE
CE HIGH to high Z[13, 14]
–
20
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
tLZBE[15]
BLE/BHE LOW to low Z[13]
5
–
ns
–
20
ns
tHZBE
Write
BLE/BHE HIGH to high
Z[13, 14]
Cycle[16, 17]
tWC
Write cycle time
55
–
ns
tSCE
CE LOW to write end
40
–
ns
tAW
Address setup to write end
40
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tBW
BLE/BHE LOW to write end
40
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z[13, 14]
–
20
ns
10
–
ns
tLZWE
WE HIGH to low
Z[13]
Notes
11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both byte enable pins.
12. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL.
13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
17. The minimum write pulse width for WRITE Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 38-05229 Rev. *R
Page 7 of 17
CY62127DV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [18, 19]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [18, 19, 20]
Notes
18. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
19. WE is HIGH for Read cycle.
20. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document Number: 38-05229 Rev. *R
Page 8 of 17
CY62127DV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [21, 22, 23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
DON'T CARE
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled) [21, 22, 23, 24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE / BLE
OE
tSD
DATA I/O
tHD
DATA IN VALID
DON'T CARE
tHZOE
Notes
21. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
22. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
23. Data I/O is high-impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
25. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05229 Rev. *R
Page 9 of 17
CY62127DV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [26, 27, 28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
tHD
DATAIN VALID
DON'T CARE
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE / BLE Controlled) [26, 27]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
DON'T CARE
tHD
DATAIN VALID
Notes
26. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
27. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
28. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 38-05229 Rev. *R
Page 10 of 17
CY62127DV30 MoBL®
Truth Table
CE [29, 30]
WE
OE
BHE
BLE
H
X
X
X
X
High Z
High Z
Deselect/Power-down Standby (ISB)
L
X
X
H
H
High Z
High Z
Deselect/Power-down Standby (ISB)
L
H
L
L
L
Data Out
Data Out
Read All Bits
L
H
L
H
L
Data Out
High Z
Read Lower Byte Only Active (ICC)
L
H
L
L
H
High Z
Data Out
Read Upper Byte Only Active (ICC)
L
H
H
L
L
High Z
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data in
Data in
Write
Active (ICC)
L
L
X
H
L
Data in
High Z
Write Lower Byte Only Active (ICC)
L
L
X
L
H
High Z
Data in
Write Upper Byte Only Active (ICC)
I/O0–I/O7
I/O8–I/O15
Mode
Power
Active (ICC)
Notes
29. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
30. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05229 Rev. *R
Page 11 of 17
CY62127DV30 MoBL®
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and see
product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
55
Ordering Code
CY62127DV30LL-55BVXI
Package
Diagram
Package Type
51-85150 48-ball FBGA (6 mm × 8 mm × 1 mm) (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 2
7
D V30 LL - 55 XX X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV
BV = 48-ball FBGA
Speed Grade: 55 = 55 ns
LL = Low Power
Voltage Range: V30 = 3 V typical
Process Technology: D = 130 nm
Bus Width: 7 = × 16
Density: 2 = 1-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05229 Rev. *R
Page 12 of 17
CY62127DV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05229 Rev. *R
Page 13 of 17
CY62127DV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
µA
microampere
CE
Chip Enable
mA
milliampere
FBGA
Fine-Pitch Ball Grid Array
ns
nanosecond
I/O
Input/Output
pF
picofarad
OE
Output Enable
V
volt
SRAM
Static Random Access Memory
W
watt
TSOP
Thin Small Outline Package
WE
Write Enable
Document Number: 38-05229 Rev. *R
Symbol
Unit of Measure
Page 14 of 17
CY62127DV30 MoBL®
Document History Page
Document Title: CY62127DV30 MoBL®, 1-Mbit (64K × 16) Static RAM
Document Number: 38-05229
Revision
ECN
Orig. of
Change
Submission
Date
**
117690
JUI
08/27/02
New data sheet
*A
127311
MPR
06/13/03
Changed status from Advanced to Preliminary.
Updated DC Electrical Characteristics:
Changed maximum value of ISB2 parameter from 4 µA to 5 µA corresponding
to Test Condition “L”.
Changed maximum value of ISB2 parameter from 3 µA to 4 µA corresponding
to Test Condition “LL”.
Updated Capacitance:
Changed value of CIN parameter from 6 pF to 8 pF.
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 1.2 µA to 4 µA
corresponding to Test Condition “L”.
Changed maximum value of ICCDR parameter from 0.8 µA to 3 µA
corresponding to Test Condition “LL”.
*B
128341
JUI
07/22/03
Changed status from Preliminary to Final.
Add 70 ns speed related information in all instances across the document.
Updated Ordering Information.
*C
129000
CDY
08/29/03
Updated DC Electrical Characteristics:
Changed typical value of ICC parameter corresponding to Test Condition
“f = 1 MHz” from 0.5 mA to 0.85 mA.
*D
316039
PCI
See ECN
Added 45 ns speed bin related information in all instances across the
document.
Updated AC Test Loads and Waveforms:
Added Note “Test condition for the 45-ns part is a load capacitance of 30 pF.”
and referred the same note in Figure 3.
Updated Ordering Information:
Updated part numbers.
Changed name of 44-lead TSOP-II package from Z44 to ZS44 in “Package
Name” column.
*E
346982
AJU
See ECN
Added 56-pin QFN package related information in all instances across the
document.
Updated Ordering Information.
*F
369955
SYT
See ECN
Added Automotive related information in all instances across the document.
Updated Features:
Added Temperature Ranges.
Updated Ordering Information:
Added Pb-free Automotive parts for 55 ns Speed bin.
*G
457685
NXR
See ECN
Removed 56-pin QFN package related information in all instances across the
document.
Updated Ordering Information.
*H
470383
NXR
See ECN
Updated Pin Configurations:
Updated Figure 2 (Changed pin 23 of TSOP II from NC to DNU).
Updated Note 3.
*I
2897885
RAME /
NIKM
03/22/10
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
Document Number: 38-05229 Rev. *R
Description of Change
Page 15 of 17
CY62127DV30 MoBL®
Document History Page (continued)
Document Title: CY62127DV30 MoBL®, 1-Mbit (64K × 16) Static RAM
Document Number: 38-05229
Revision
ECN
Orig. of
Change
Submission
Date
*J
3010373
AJU
08/20/2010
*K
3329789
RAME
07/27/11
Updated Functional Description:
Removed the Note “For best practice recommendations, refer to the Cypress
application note “System Design Guidelines” at http://www.cypress.com
website.” and its reference.
Updated to new template.
Post to web.
Description of Change
Updated Features.
Updated Product Portfolio.
Updated Operating Range.
Updated DC Electrical Characteristics.
Updated Data Retention Characteristics.
Updated Switching Characteristics.
Updated Ordering Information and added Ordering Code Definitions.
Minor edits.
Updated to new template.
*L
3393183
RAME
10/03/11
*M
3861271
TAVA
01/08/2013
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85087 – Changed revision from *D to *E.
*N
4499469
MEMJ
09/11/2014
Updated Switching Characteristics:
Added Note 17 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 28 and referred the same note in Figure 9.
Updated to new template.
Completing Sunset Review.
*O
4576478
MEMJ
11/21/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*P
4920942
VINI
09/15/2015
Updated to new template.
Completing Sunset Review.
*Q
5444200
VINI
09/21/2016
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated all values of JA and JC parameters.
Updated to new template.
Completing Sunset Review.
*R
5997966
AESATMP9
12/21/2017
Updated logo and copyright.
Document Number: 38-05229 Rev. *R
Page 16 of 17
CY62127DV30 MoBL®
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© Cypress Semiconductor Corporation, 2002-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 38-05229 Rev. *R
Revised December 21, 2017
Page 17 of 17
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