CY62128EV30LL-45ZXI

CY62128EV30 MoBL® 1 Mbit (128K x 8) Static RAM Features ■ ■ Functional Description The CY62128EV30[1] is a high performance CMOS static RAM module organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 through A16). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Very High Speed: 45 ns Temperature Ranges: ❐ Industrial: –40°C to +85°C ❐ Automotive-A: –40°C to +85°C ❐ Automotive-E: –40°C to +125°C Wide Voltage Range: 2.2 V to 3.6 V Pin Compatible with CY62128DV30 Ultra Low Standby Power ❐ Typical standby current: 1 μA ❐ Maximum standby current: 4 μA Ultra Low Active Power ❐ Typical active current: 1.3 mA @ f = 1 MHz Easy Memory Expansion with CE1, CE2 and OE Features Automatic Power Down when Deselected CMOS for Optimum Speed and Power Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin STSOP Packages ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WE OE INPUT BUFFER IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6 ROW DECODER 128K x 8 ARRAY COLUMN DECODER POWER DOWN IO7 A12 A13 A14 A15 Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. A16 Cypress Semiconductor Corporation Document #: 38-05579 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 05, 2009 [+] Feedback CY62128EV30 MoBL® Pin Configuration Figure 1. 24-Pin STSOP [2] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 Figure 2. 32-Pin TSOP I [2] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 STSOP Top View (not to scale) TSOP I Top View (not to scale) Figure 3. 32-Pin SOIC [2] Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO 0 IO 1 IO 2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 IO 7 IO 6 IO 5 IO 4 IO 3 Table 1. Product Portfolio Power Dissipation Product Range Min CY62128EV30LL Industrial/Auto-A CY62128EV30LL Auto-E 2.2 2.2 VCC Range (V) Typ[3] 3.0 3.0 Max 3.6 3.6 45 55 Speed (ns) Typ[3] 1.3 1.3 Operating ICC (mA) f = 1 MHz Max 2.0 4.0 f = fmax Typ[3] 11 11 Max 16 35 Standby ISB2 (µA) Typ[3] 1 1 Max 4 30 Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05579 Rev. *E Page 2 of 12 [+] Feedback CY62128EV30 MoBL® Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground Potential..........................................–0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[4, 5] .........................–0.3V to VCC(max) + 0.3V DC Input Voltage[4,5] .......................–0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Device CY62128EV30LL Range Ind’l/Auto-A Auto-E Ambient Temperature –40°C to +85°C –40°C to +125°C VCC[6] 2.2V to 3.6V Electrical Characteristics (Over the Operating Range) Parameter VOH Description Output HIGH Voltage Test Conditions IOH = –0.1 mA IOH = –1.0 mA, VCC > 2.70V VOL VIH Output LOW Voltage Input HIGH Voltage IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VIL IIX IOZ ICC Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA f = 1 MHz CMOS levels 1.8 2.2 –0.3 –0.3 –1 –1 11 1.3 1 45 ns (Industrial/Auto-A) Min 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 16 2.0 4 1.8 2.2 –0.3 –0.3 –4 –4 11 1.3 1 Typ[3] Max 55 ns (Auto-E) Min 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +4 +4 35 4.0 35 Typ[3] Max Unit V V V V V V V V μA μA mA mA μA ISB1 CE1 > VCC−0.2V, CE2 < 0.2V Automatic CE Power down VIN > VCC–0.2V, VIN < 0.2V) Current — CMOS Inputs f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60V Automatic CE CE1 > VCC – 0.2V, CE2 < 0.2V Power down VIN > VCC – 0.2V or VIN < 0.2V, Current — CMOS Inputs f = 0, VCC = 3.60V ISB2[7] 1 4 1 30 μA Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization. 7. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05579 Rev. *E Page 3 of 12 [+] Feedback CY62128EV30 MoBL® Capacitance (For all packages)[8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP I 33.01 3.42 SOIC 48.67 25.86 STSOP 32.56 3.59 Unit °C/W °C/W Figure 4. AC Test Loads and Waveforms R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% VCC OUTPUT ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 RTH V 3.0V 1103 1554 645 1.75 Unit Ω Ω Ω V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR[7] Description VCC for Data Retention Data Retention Current VCC = 1.5V, CE1 > VCC − 0.2V or CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V Industrial/Auto-A Auto-E 0 tRC Conditions Min 1.5 3 30 Typ[3] Max Unit V μA μA ns ns tCDR[8] tR[9] Chip Deselect to Data Retention Time Operation Recovery Time Note 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. Document #: 38-05579 Rev. *E Page 4 of 12 [+] Feedback CY62128EV30 MoBL® Figure 5. Data Retention Waveform [10] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE Switching Characteristics (Over the Operating Range)[10, 11] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[14] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z [12, 13] [12] Description 45 ns (Industrial/Auto-A) Min 45 45 10 45 22 5 18 10 18 0 45 45 35 35 0 0 35 25 0 18 10 Max 55 ns (Auto-E) Min 55 55 10 55 25 5 20 10 20 0 55 55 40 40 0 0 40 25 0 20 10 Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[12] Z[12,13] [12] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High CE LOW to Low Z CE HIGH to High Z[12, 13] CE LOW to Power Up CE HIGH to Power Down Notes 10. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05579 Rev. *E Page 5 of 12 [+] Feedback CY62128EV30 MoBL® Switching Waveforms Figure 6. Read Cycle 1 (Address transition controlled) [15, 16] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 7. Read Cycle No. 2 (OE controlled) [10, 16, 17] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Figure 8. Write Cycle No. 1 (WE controlled) [10, 15, 18, 19] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 20 tHZOE Notes 15. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 18. Data I/O is high impedance if OE = VIH. 19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals. tHD DATA VALID Document #: 38-05579 Rev. *E Page 6 of 12 [+] Feedback CY62128EV30 MoBL® Switching Waveforms (continued) Figure 9. Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19] tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA CE Figure 10. Write Cycle No. 3 (WE controlled, OE LOW) [10, 19] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 20 tHZWE DATA VALID tPWE tHA tHD tLZWE Table 2. Truth Table for CY62128EV30 CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X Inputs/Outputs High Z High Z Data Out High Z Data in Mode Deselect/Power Down Deselect/Power Down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05579 Rev. *E Page 7 of 12 [+] Feedback CY62128EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62128EV30LL-45SXI CY62128EV30LL-45ZXI CY62128EV30LL-45ZAXI 45 55 CY62128EV30LL-45SXA CY62128EV30LL-45ZXA CY62128EV30LL-55ZXE Package Diagram Package Type Operating Range Industrial 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) 51-85094 32-pin STSOP (Pb-free) 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) Automotive-E Automotive-A Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 11. 32-Pin (450 Mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B Document #: 38-05579 Rev. *E Page 8 of 12 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 12. 32-Pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056 51-85056-*D Document #: 38-05579 Rev. *E Page 9 of 12 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 13. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 51-85094-*D Document #: 38-05579 Rev. *E Page 10 of 12 [+] Feedback CY62128EV30 MoBL® Document History Page Document Title: CY62128EV30 MoBL® 1 Mbit (128K x 8) Static RAM Document Number: 38-05579 REV. ** *A ECN NO. Issue Date 285473 461631 See ECN See ECN Orig. of Change PCI NXR New Data Sheet Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62128EV30 Removed Reverse TSOP I package from Product offering. Changed ICC (Typ) from 8 mA to 11 mA and ICC (Max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Changed ISB2 (max) from 1 μA to 4 μA Changed ISB2 (Typ) from 0.5 μA to 1 μA Changed ICCDR (max) from 1 μA to 3 μA Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information table. Updated the Block Diagram on page # 1 Added final Automotive-A and Automotive-E information Added footnote #9 related to ISB2 and ICCDR Updated Ordering Information table Changed the Maximum rating of Ambient Temperature with Power Applied from 55°C to +125°C to –55°C to +125°C. Description of Change *B *C 464721 1024520 See ECN See ECN NXR VKN *D *E 2257446 2702841 See ECN NXR 05/06/2009 VKN/PYRS Added -45SXA part in the Ordering Information table Corrected “tPD” spec description in the “Switching Characteristics” table. Document #: 38-05579 Rev. *E Page 11 of 12 [+] Feedback CY62128EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05579 Rev. *E Revised May 05, 2009 Page 12 of 12 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback