CY62128EV30LL

CY62128EV30 MoBL® 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features ■ ■ Functional Description The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). To write to the device, take chip enable (CE1 LOW and CE2 HIGH) and write enable (WE) inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pin (A0 through A16). To read from the device, take chip enable (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Very high speed: 45 ns Temperature ranges: ❐ Industrial: –40 °C to +85 °C Wide voltage range: 2.2 V to 3.6 V Pin compatible with CY62128DV30 Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 4 µA Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Offered in Pb-free 32-pin SOIC, 32-pin thin small outline package (TSOP) Type I, and 32-pin shrunk thin small outline package (STSOP) packages ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WE OE INPUT BUFFER I/O 0 I/O 1 SENSE AMPS I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ROW DECODER 128K x 8 ARRAY COLUMN DECODER POWER DOWN I/O 7 A12 A14 A13 A16 A15 Cypress Semiconductor Corporation Document #: 38-05579 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 25, 2011 [+] Feedback CY62128EV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Document #: 38-05579 Rev. *J Page 2 of 18 [+] Feedback CY62128EV30 MoBL® Pin Configuration Figure 1. 32-pin STSOP [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Figure 2. 32-pin TSOP I [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Top View (not to scale) Top View (not to scale) Figure 3. 32-pin SOIC [1] Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Product Portfolio Power Dissipation Product Range Min CY62128EV30LL Industrial 2.2 VCC Range (V) Typ [2] 3.0 Max 3.6 45 Speed (ns) Typ [2] 1.3 Operating ICC (mA) f = 1 MHz Max 2.0 11 f = fmax Typ [2] Max 16 Standby ISB2 (µA) Typ [2] 1 Max 4 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05579 Rev. *J Page 3 of 18 [+] Feedback CY62128EV30 MoBL® Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage to ground potential .......................................–0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in high Z State [3, 4] ......................–0.3 V to VCC(max) + 0.3 V DC input voltage [3, 4] ...................–0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch-up current .................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC[5] CY62128EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1[7] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Test Conditions IOH = –0.1 mA IOH = –1.0 mA, VCC > 2.70 V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, output disabled f = fmax = 1/tRC f = 1 MHz Automatic CE power-down current — CMOS inputs Automatic CE power-down current — CMOS inputs VCC = VCCmax IOUT = 0 mA CMOS levels 45 ns (Industrial) Min 2.0 2.4 – – 1.8 2.2 –0.3 –0.3 –1 –1 – – – Typ [6] – – – – – – – – – – 11 1.3 1 Max – – 0.4 0.4 VCC + 0.3 V VCC + 0.3 V 0.6 0.8 +1 +1 16 2.0 4 Unit V V V V V V V V µA µA mA mA µA CE1 > VCC0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V, VIN < 0.2 V f = fmax (address and data only), f = 0 (OE and WE), VCC = 3.60 V CE1 > VCC – 0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V ISB2[7] – 1 4 µA Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05579 Rev. *J Page 4 of 18 [+] Feedback CY62128EV30 MoBL® Capacitance Parameter [8] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Parameter [8] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 32-pin TSOP I 33.01 3.42 32-pin SOIC 48.67 25.86 32-pin STSOP Unit 32.56 3.59 °C/W °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V Parameters R1 R2 RTH VTH 2.50 V 16667 15385 8000 1.20 3.0 V 1103 1554 645 1.75 Unit    V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05579 Rev. *J Page 5 of 18 [+] Feedback CY62128EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR[10] Description VCC for data retention Data retention current VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Industrial Conditions Min 1.5 – Typ [9] – – Max – 3 Unit V µA tCDR[11] tR[12] Chip deselect to data retention time Operation recovery time 0 45 – – – – ns ns Data Retention Waveform Figure 5. Data Retention Waveform [13] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min)  100 µs. 13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 38-05579 Rev. *J Page 6 of 18 [+] Feedback CY62128EV30 MoBL® Switching Characteristics Over the Operating Range Parameter [14, 15] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle [18] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z [16, 17] Description 45 ns (Industrial) Min 45 – 10 – – 5 – 10 – 0 – 45 35 35 0 0 35 25 0 – 10 Max – 45 – 45 22 – 18 – 18 – 45 – – – – – – – – 18 – Unit Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z [16] OE HIGH to high Z [16, 17] CE LOW to low Z [16] CE HIGH to high Z [16, 17] CE LOW to power-up CE HIGH to power-down ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns WE HIGH to low Z [16] Notes 14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05579 Rev. *J Page 7 of 18 [+] Feedback CY62128EV30 MoBL® Switching Waveforms Figure 6. Read Cycle 1 (Address Transition Controlled) [20, 21] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 7. Read Cycle No. 2 (OE Controlled) [21, 22, 23] 2 ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 20. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 21. WE is HIGH for read cycle. 22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 23. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 38-05579 Rev. *J Page 8 of 18 [+] Feedback CY62128EV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled) [24, 25, 26, 27] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 28 tHZOE DATA VALID tHD Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [24, 25, 26, 27] tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA CE Notes 24. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 25. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 26. Data I/O is high impedance if OE = VIH. 27. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05579 Rev. *J Page 9 of 18 [+] Feedback CY62128EV30 MoBL® Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [29, 30] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 31 tHZWE DATA VALID tPWE tHA tHD tLZWE Notes 29. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 31. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05579 Rev. *J Page 10 of 18 [+] Feedback CY62128EV30 MoBL® Truth Table CE1 H X [32] CE2 X [32] WE X X H L H OE X X L X H Inputs/Outputs High Z High Z Data out Data in High Z Mode Deselect/power-down Deselect/power-down Read Write Selected, outputs disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) L H H H L L L Note 32. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 38-05579 Rev. *J Page 11 of 18 [+] Feedback CY62128EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62128EV30LL-45SXI CY62128EV30LL-45ZXI CY62128EV30LL-45ZAXI Package Diagram Package Type Operating Range Industrial 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) 51-85094 32-pin STSOP (Pb-free) Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 2 8 E V30 LL - 45 XX X I Temperature Grade: I = Industrial Pb-free Package Type: XX = S or Z or ZA S = 32-pin SOIC Z = 32-pin TSOP Type I ZA = 32-pin STSOP Speed Grade: 45 ns LL = Low Power Voltage Range: 3 V typical E = Process Technology 90 nm Bus width = × 8 Density = 1-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 38-05579 Rev. *J Page 12 of 18 [+] Feedback CY62128EV30 MoBL® Package Diagrams Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081 51-85081 *C Document #: 38-05579 Rev. *J Page 13 of 18 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056 51-85056 *F Document #: 38-05579 Rev. *J Page 14 of 18 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 13. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094 51-85094 *F Document #: 38-05579 Rev. *J Page 15 of 18 [+] Feedback CY62128EV30 MoBL® Acronyms Acronym BHE BLE CE CMOS I/O OE SOIC SRAM STSOP TSOP WE byte high enable byte low enable chip enable complementary metal oxide semiconductor input/output output enable small outline integrated circuit static random access memory shrunk thin small outline package thin small outline package write enable Description Document Conventions Units of Measure Symbol °C MHz A s mA mm ns  % pF V W degree Celsius Mega Hertz micro Amperes micro seconds milli Amperes milli meter nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document #: 38-05579 Rev. *J Page 16 of 18 [+] Feedback CY62128EV30 MoBL® Document History Page Document Title: CY62128EV30 MoBL®, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05579 Rev. ** *A ECN No. 285473 461631 Submission Date See ECN See ECN Orig. of Change PCI NXR New Data Sheet Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62128EV30 Removed Reverse TSOP I package from Product offering. Changed ICC (Typ) from 8 mA to 11 mA and ICC (Max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Changed ISB2 (max) from 1 A to 4 A Changed ISB2 (Typ) from 0.5 A to 1 A Changed ICCDR (max) from 1 A to 3 A Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information table. Updated the Block Diagram on page # 1 Added final Automotive-A and Automotive-E information Added footnote #9 related to ISB2 and ICCDR Updated Ordering Information table Changed the Maximum rating of Ambient Temperature with Power Applied from 55°C to +125°C to –55°C to +125°C. Description of Change *B *C 464721 1024520 See ECN See ECN NXR VKN *D *E *F *G 2257446 2702841 2781490 2934428 See ECN 05/06/2009 10/08/2009 06/03/10 NXR VKN/PYRS Added -45SXA part in the Ordering Information table Corrected “tPD” spec description in the “Switching Characteristics” table. VKN VKN Included “CY62128EV30LL-45ZAXA” part in the Ordering Information table Added footnote #21 related to chip enable Updated package diagrams Updated template Updated Pin Configuration Added Ordering Code Definitions Added Acronyms and Units of Measure Minor edits Separated Automotive and Industrial parts from this datasheet. Removed Automotive info completely Removed the Note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.” and its reference in Functional Description. Updated Package Diagrams. Updated in new template. *H 3026548 09/12/2010 AJU *I *J 3115909 3292906 01/06/2011 06/25/2011 RAME AJU Document #: 38-05579 Rev. *J Page 17 of 18 [+] Feedback CY62128EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05579 Rev. *J Revised June 25, 2011 Page 18 of 18 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback