CY62136EV30LL-45BVXI

CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAM Features ■ ■ ■ ■ Functional Description The CY62136EV30[1] is a high performance CMOS static RAM organized as 128 K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appear on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. Very high speed: 45 ns Wide voltage range: 2.20 V to 3.60 V Pin compatible with CY62136CV30 Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed/power Offered in a Pb-free 48-ball very fine ball grid array (VFBGA) and 44-pin thin small outline package (TSOP II) packages ■ ■ ■ ■ ■ Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 128K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A11 A12 Note 1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com. A13 A14 A15 A16 Cypress Semiconductor Corporation Document #: 38-05569 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 17, 2011 [+] Feedback CY62136EV30 MoBL® Contents Pin Configuration .............................................................. 3 Product Portfolio ............................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics.................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics................................................. 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Document #: 38-05569 Rev. *D Page 2 of 15 [+] Feedback CY62136EV30 MoBL® Pin Configuration[2, 3] VFBGA (Top View) 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 I/O12 I/O13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44 TSOP II (Top View) A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Product Portfolio[4] Power Dissipation Product Min CY62136EV30LL 2.2 VCC Range (V) Typ[4] 3.0 Max 3.6 45 Speed (ns) Typ[4] 2 Operating ICC (mA) f = 1 MHz Max 2.5 f = fmax Typ[4] 15 Max 20 Standby ISB2 (A) Typ[4] 1 Max 7 Notes 2. NC pins are not connected on the die. 3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document #: 38-05569 Rev. *D Page 3 of 15 [+] Feedback CY62136EV30 MoBL® Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential ........................... –0.3 V to 3.9 V (VCC MAX + 0.3 V) DC voltage applied to outputs in High-Z state[5,6] .............. –0.3 V to 3.9 V (VCC MAX + 0.3 V) DC input voltage[5,6] ........... –0.3 V to 3.9 V (VCC MAX + 0.3 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage ......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch up current ..................................................... > 200 mA Operating Range Device Range Ambient Temperature –40 °C to +85 °C VCC[7] 2.2 V - 3.6 V CY62136EV30LL Industrial Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 [9] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Automatic CE power-down current — CMOS inputs Automatic CE power-down current — CMOS inputs Test Conditions IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1 mA VCC = 2.20 V VCC = 2.70 V VCC = 2.20 V VCC = 2.70 V 45 ns Min 2.0 2.4 – – 1.8 2.2 –0.3 –0.3 –1 –1 – – – Typ[8] – – – – – – – – – – 15 2 1 Max – – 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 20 2.5 7 Unit V V V V V V V V A A mA A VCC = 2.2V to 2.7 V VCC= 2.7 V to 3.6 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, output disabled f = fmax = 1/tRC f = 1 MHz VCC = VCCmax, IOUT = 0 mA CMOS levels CE > VCC0.2 V, VIN>VCC–0.2 V, VIN VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2V, f = 0, VCC = 3.60 V ISB2 [9] – 1 7 A Capacitance Parameter[10] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 5. VIL(min.) = –2.0 V for pulse durations less than 20 ns. 6. VIH(max)=VCC+0.75 V for pulse durations less than 20 ns. 7. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C 9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05569 Rev. *D Page 4 of 15 [+] Feedback CY62136EV30 MoBL® Thermal Resistance Parameter[11] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 1. AC Test Loads and Waveforms VCC OUTPUT R1 VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board VFBGA Package 75 10 TSOP II Package 77 13 Unit C / W C / W 30 pF INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH 2.50 V 16667 15385 8000 1.20 3.0 V 1103 1554 645 1.75 Unit    V Parameters R1 R2 RTH VTH Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR [13] Description VCC for data retention Data retention current Conditions VCC= 1.0 V CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min 1.0 – Typ[12] – 0.8 Max – 3 Unit V A tCDR[11] tR[14] Chip deselect to data retention time Operation recovery time 0 45 – – – ns ns Data Retention Waveform[15] VCC VCC(min) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min) tR CE Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C 13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating 14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 15. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05569 Rev. *D Page 5 of 15 [+] Feedback CY62136EV30 MoBL® Switching Characteristics Over the Operating Range Parameter[16, 17] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[20] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to High Z [18, 19] Description 45 ns Min 45 – 10 – – 5 – 10 – 0 – – 5 – 45 35 35 0 0 35 35 25 0 – 10 Max – 45 – 45 22 – 18 – 18 – 45 22 – 18 – – – – – – – – – 18 – Unit Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to LOW Z[18] OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z [18, 19] [18] [18, 19] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE LOW to power-up CE HIGH to power-down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z [18] BLE/BHE HIGH to HIGH Z[18, 19] WE HIGH to Low Z[18] Notes 16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms. 17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note AN13842 for more information. 18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 20. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05569 Rev. *D Page 6 of 15 [+] Feedback CY62136EV30 MoBL® Switching Waveforms Figure 2. Read Cycle 1: Address Transition Controlled [21, 22] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID Figure 3. Read Cycle No. 2 : OE Controlled[22, 23] tAA DATA VALID ADDRESS CE tACE OE tDOE BHE/BLE tLZOE tRC tPD tHZCE tHZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE . Notes 21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 22. WE is HIGH for read cycle. 23. Address valid prior to or coincident with CE and BHE, BLE transition LOW. Document #: 38-05569 Rev. *D Page 7 of 15 [+] Feedback CY62136EV30 MoBL® Switching Waveforms (continued) Figure 4. Write Cycle No. 1: WE Controlled [24, 25, 26] tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 27 tHZOE DATAIN tHD Figure 5. Write Cycle No. 2: CE Controlled [24, 25, 26] tWC ADDRESS tSCE CE tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA I/O NOTE 27 tHZOE Notes 24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 25. Data I/O is high impedance if OE = VIH. 26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state and input signals should not be applied. tHD DATAIN Document #: 38-05569 Rev. *D Page 8 of 15 [+] Feedback CY62136EV30 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 3: WE Controlled, OE LOW [28] tWC ADDRESS tSCE CE tBW tAW tSA WE tSD DATA I/O NOTE 29 tHZWE DATAIN tLZWE tHD tPWE tHA BHE/BLE Figure 7. Write Cycle No. 4: BHE/BLE Controlled, OE LOW [28] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tHZWE tHA tBW tPWE tSD DATAIN tLZWE tHD DATA I/O NOTE 29 Notes 28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state 29. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05569 Rev. *D Page 9 of 15 [+] Feedback CY62136EV30 MoBL® Truth Table CE H[30] L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X[30] H L H L L H L L H L BLE X[30] H L L H L L H L L H Inputs/Outputs High Z High Z Data out (I/OO–I/O15) Data out (I/OO–I/O7); I/O8–I/O15 in High Z Data Out (I/O8–I/O15); I/O0–I/O7 in High Z High Z High Z High Z Data in (I/OO–I/O15) Data in (I/OO–I/O7); I/O8–I/O15 in High Z Data in (I/O8–I/O15); I/O0–I/O7 in High Z Mode Deselect/power-down Output disabled Read Read Read Output disabled Output disabled Output disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Note 30. Chip enable (CE) and Byte enables (BHE and BLE) must be at fixed CMOS levels (not floating). Intermediate voltage levels on these pins is not permitted Document #: 38-05569 Rev. *D Page 10 of 15 [+] Feedback CY62136EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62136EV30LL-45BVXI CY62136EV30LL-45ZSXI Package Diagram 51-85150 51-85087 Package Type 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) 44-Pin Thin Small Outline Package II (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of other parts Ordering Code Definition CY 621 3 6E V30 LL 45 XXX I Temperature Grades I = Industrial Package Type BVX: VFBGA (Pb-free) ZSX : TSOP II (Pb-free) Speed Grade Low Power Wide Voltage Range (3 V and 5 V) Bus Width = X16 E = 90nm Technology Density = 2 Mbit MoBL SRAM Family Company ID: CY = Cypress Document #: 38-05569 Rev. *D Page 11 of 15 [+] Feedback CY62136EV30 MoBL® Package Diagrams Figure 8. 48-Pin VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*F Document #: 38-05569 Rev. *D Page 12 of 15 [+] Feedback CY62136EV30 MoBL® Package Diagrams (continued) Figure 9. 44-Pin TSOP II (51-85087) 51-85087-*C Acronyms Acronym CMOS I/O SRAM VFBGA TSOP input/output static random access memory very fine ball gird array thin small outline package Description complementary metal oxide semiconductor Document Conventions Units of Measure Symbol °C A mA MHz ns pF V  W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts Document #: 38-05569 Rev. *D Page 13 of 15 [+] Feedback CY62136EV30 MoBL® Document History Page Document Title: CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAM Document Number: 38-05569 Rev. ** *A ECN No. 237432 419988 Orig. of Change AJU RXU Submission Date See ECN See ECN Description of Change New Data Sheet Converted from Advanced Information to Final. Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62136EV30 Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from 2.5 A to 7 A. Changed the AC test load capacitance from 50pF to 30pF on Page# 4 Changed VDR from 1.5V to 1V on Page# 4. Changed ICCDR from 2.5 A to 3 A. Added ICCDR typical value. Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns Changed tLZBE from 6 ns to 5 ns Changed tLZOE from 3 ns to 5 ns Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns Changed tSCE,tAW and tBW from 40 ns to 35 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Corrected typo in the Truth Table on Page# 9 Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering Information table and replaced the Package Name column with Package Diagram. Minor change: Moved datasheet to external web Added footnote 8 related to ISB2 and ICCDR Added footnote 12 related to AC timing parameters Added Acronyms and Units of Measure table Added Ordering Code Definition Update Package Diagrams 51-85150 from *D to *F Converted all tablenotes into footnotes Added TOC Updated datasheet as per new template. *B *C *D 427817 2604685 3144174 NXR VKN/PYRS RAME See ECN 11/12/08 01/17/2011 Document #: 38-05569 Rev. *D Page 14 of 15 [+] Feedback CY62136EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05569 Rev. *D Revised January 17, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback