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CY62136EV30 MoBL®
2-Mbit (128K × 16) Static RAM
2-Mbit (128K × 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62136CV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
The CY62136EV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. The device can
also be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high impedance state
when: deselected (CE HIGH), outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE LOW).
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■
Offered in a Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP II) packages
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A16). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appear on I/O8 to I/O15. See the Truth Table on page 11
for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
128K x 16
RAM Array
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document Number: 38-05569 Rev. *J
•
BHE
WE
CE
OE
BLE
A13
A14
A15
A16
A11
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 11, 2017
CY62136EV30 MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 38-05569 Rev. *J
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Page 2 of 18
CY62136EV30 MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1, 2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
Vcc
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
Figure 2. 44-pin TSOP II pinout (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Product Portfolio
Power Dissipation
VCC Range (V)
Product [3]
CY62136EV30LL
Speed
(ns)
Min
Typ [3]
Max
2.2
3.0
3.6
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
Document Number: 38-05569 Rev. *J
Page 3 of 18
CY62136EV30 MoBL®
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage
to ground potential [4, 5] ... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
DC voltage applied to outputs
in High Z state [4, 5] .......... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Device
CY62136EV30LL
Range
Ambient
Temperature
VCC[6]
Industrial –40 °C to +85 °C 2.2 V–3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Output HIGH voltage
VOH
Output LOW voltage
VOL
Input HIGH voltage
VIH
Input LOW voltage
VIL
Test Conditions
45 ns
Min
Typ [7]
Max
Unit
IOH = –0.1 mA
VCC = 2.20 V
2.0
–
–
V
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
–
15
20
mA
–
2
2.5
–
1
7
A
–
1
7
A
f = 1 MHz
ISB1[8]
Automatic CE power-down
current – CMOS inputs
VCC = VCCmax,
IOUT = 0 mA
CMOS levels
CE > VCC0.2 V,
VIN > VCC – 0.2 V, VIN< 0.2 V
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
ISB2
[8]
Automatic CE power-down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2V, f = 0,
VCC = 3.60 V
Notes
4. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ISB2/ICCDR specification. Other inputs can be left floating.
Document Number: 38-05569 Rev. *J
Page 4 of 18
CY62136EV30 MoBL®
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
54
57
C/W
12
17
C/W
AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
VCC
90%
90%
10%
10%
GND
R2 Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50 V
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05569 Rev. *J
Page 5 of 18
CY62136EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
VCC for data retention
[11]
Data retention current
VCC= 1.0 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min
Typ [10]
Max
Unit
1.0
–
–
V
–
0.8
3
A
tCDR[12]
Chip deselect to data
retention time
0
–
–
ns
tR[13]
Operation recovery time
45
–
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.0 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05569 Rev. *J
Page 6 of 18
CY62136EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[17]
5
–
ns
–
18
ns
tLZOE
tHZOE
OE LOW to Low Z
OE HIGH to High Z
[17, 18]
[17]
tLZCE
CE LOW to Low Z
10
–
ns
tHZCE
CE HIGH to High Z [17, 18]
–
18
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
22
ns
tLZBE
BLE/BHE LOW to Low Z [17]
5
–
ns
–
18
ns
tHZBE
Write Cycle
BLE/BHE HIGH to High Z
[17, 18]
[19, 20]
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High Z [17, 18]
–
18
ns
10
–
ns
tLZWE
WE HIGH to Low Z
[17]
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in Figure 3 on page 5.
16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
20. The minimum write pulse for Write Cycle No. 3 (WE Controlled and OE LOW) should be sum of tHZWE and tSD.
Document Number: 38-05569 Rev. *J
Page 7 of 18
CY62136EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled [21, 22]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2: OE Controlled [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
.
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document Number: 38-05569 Rev. *J
Page 8 of 18
CY62136EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1: WE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 27
tHD
DATAIN
tHZOE
Figure 8. Write Cycle No. 2: CE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 27
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05569 Rev. *J
Page 9 of 18
CY62136EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3: WE Controlled, OE LOW [28, 29]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATAI/O
NOTE 30
tHD
DATAIN
tHZWE
tLZWE
Figure 10. Write Cycle No. 4: BHE/BLE Controlled, OE LOW [28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 30
tSD
tHD
DATAIN
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
30. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05569 Rev. *J
Page 10 of 18
CY62136EV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
H[31]
X
X
X[31]
X[31]
High Z
Inputs/Outputs
Deselect/power-down
Mode
Standby (ISB)
Power
L
X
X
H
H
High Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
31. Chip enable (CE) and Byte enables (BHE and BLE) must be at fixed CMOS levels (not floating). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05569 Rev. *J
Page 11 of 18
CY62136EV30 MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62136EV30LL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
CY62136EV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
CY 621 3
6
E V30 LL - 45 XX X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width: 6 = × 16
Density: 3 = 2-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05569 Rev. *J
Page 12 of 18
CY62136EV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 38-05569 Rev. *J
Page 13 of 18
CY62136EV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05569 Rev. *J
Page 14 of 18
CY62136EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BLE
Byte Low enable
BHE
Byte High Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
mm
millimeter
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
SRAM
Static Random Access Memory
TSOP
Thin Small Outline Package
VFBGA
Very Fine-Pitch Ball Grid Array
WE
Write Enable
Document Number: 38-05569 Rev. *J
Symbol
Unit of Measure
Page 15 of 18
CY62136EV30 MoBL®
Document History Page
Document Title: CY62136EV30 MoBL®, 2-Mbit (128K × 16) Static RAM
Document Number: 38-05569
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
237432
AJU
See ECN
New data sheet.
*A
419988
RXU
See ECN
Changed status from Advanced Information to Final.
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62136EV30
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA
to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from
2.5 A to 7 A.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2.5 A to 3 A.
Added ICCDR typical value.
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns
Changed tSCE,tAW and tBW from 40 ns to 35 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Corrected typo in the Truth Table on Page# 9
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering Information table and replaced the Package Name
column with Package Diagram.
*B
427817
NXR
See ECN
Minor change: Moved datasheet to external web
*C
2604685
VKN /
PYRS
11/12/08
Added footnote 8 related to ISB2 and ICCDR
Added footnote 12 related to AC timing parameters
*D
3144174
RAME
01/17/2011
Added TOC
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *D to *F.
Added Acronyms and Units of Measure.
Converted all tablenotes into footnotes.
Updated to new template.
*E
3284728
AJU
06/16/2011
Removed the Note “For best practice recommendations, refer to the Cypress
application note “SRAM System Design Guidelines” on
http://www.cypress.com.” in page 1 and its reference in Functional Description.
Updated to new template.
*F
4102185
VINI
08/22/2013
Updated Switching Characteristics:
Updated Note 16.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Updated to new template.
*G
4354908
VINI
04/23/2014
Updated Switching Characteristics:
Added Note 20 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 29 and referred the same note in Figure 9.
Completing Sunset Review.
Document Number: 38-05569 Rev. *J
Description of Change
Page 16 of 18
CY62136EV30 MoBL®
Document History Page (continued)
Document Title: CY62136EV30 MoBL®, 2-Mbit (128K × 16) Static RAM
Document Number: 38-05569
Rev.
ECN No.
Orig. of
Change
Submission
Date
*H
4540616
VINI
10/16/2014
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
Updated Switching Waveforms:
Updated Note 29.
*I
4576475
VINI
11/21/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
5734096
VINI
05/11/2017
Updated Thermal Resistance:
Updated details in “Test Conditions” column and updated all values in
“48-ball BGA” and “44-pin TSOP II” columns.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05569 Rev. *J
Description of Change
Page 17 of 18
CY62136EV30 MoBL®
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
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Document Number: 38-05569 Rev. *J
Revised May 11, 2017
Page 18 of 18
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