CY62136FV30 MoBL®
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A (Industrial)
■
Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
packages
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90 percent when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or
during a write operation (CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For a complete list of related resources, click here.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
128 K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
•
A16
A15
A14
A13
A11
Cypress Semiconductor Corporation
Document Number: 001-08402 Rev. *O
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 2, 2018
CY62136FV30 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-08402 Rev. *O
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Page 2 of 18
CY62136FV30 MoBL®
Product Portfolio
Power Dissipation
Product
VCC Range (V)
Range
Min
CY62136FV30LL
Typ [1]
Max
Speed
(ns)
Operating ICC (mA)
f = 1 MHz
Standby ISB2
(A)
f = fmax
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
Industrial/Auto-A
2.2
3.0
3.6
45
1.6
2.5
13
18
1
5
Auto-E
2.2
3.0
3.6
55
2
3
15
25
1
20
Pin Configuration
Figure 1. 48-ball VFBGA pinout [2, 3]
Figure 2. 44-pin TSOP II pinout [2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
Document Number: 001-08402 Rev. *O
Page 3 of 18
CY62136FV30 MoBL®
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential [4, 5] ... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
DC voltage applied to outputs
in High Z State [4, 5] .......... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Device
Range
CY62136FV30LL Industrial/
Auto-A
Auto-E
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
Ambient
Temperature
VCC[6]
–40 °C to +85 °C 2.2 V to 3.6 V
–40 °C to +125 °C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output high voltage
2.2 < VCC < 2.7 IOH = –0.1 mA
2.7 < VCC < 3.6 IOH = –1.0 mA
VOL
Output low voltage
2.2 < VCC < 2.7 IOL = 0.1 mA
2.7 < VCC < 3.6 IOL = 2.1 mA
VIH
Input high voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
VIL
Input low voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
IIX
Input leakage current
GND < VI < VCC
IOZ
Output leakage current GND < VO < VCC, Output disabled
ICC
VCC operating supply
current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
-45 (Industrial/Auto-A)
Min
Typ
2.0
–
[7]
-55 (Auto-E)
Unit
Max
Min
Typ [7]
Max
–
2.0
–
–
V
2.4
–
–
2.4
–
–
V
–
–
0.4
–
–
0.4
V
–
–
0.4
–
–
0.4
V
1.8
–
VCC + 0.3
1.8
–
VCC + 0.3
V
2.2
–
VCC + 0.3
2.2
–
VCC + 0.3
V
–0.3
–
0.6
–0.3
–
0.6
V
–0.3
–
0.8
–0.3
–
0.8
V
–1
–
+1
–4
–
+4
A
–1
–
+1
–4
–
+4
A
–
13
18
–
15
25
mA
–
1.6
2.5
–
2
3
ISB1[8]
CE > VCC –0.2 V,
Automatic CE power
down current — CMOS VIN > VCC – 0.2 V, VIN < 0.2 V,
inputs
f = fmax (Address and data only),
f = 0 (OE, WE, BHE, and BLE),
VCC = 3.60 V
–
1
5
–
1
20
A
ISB2 [8]
CE > VCC – 0.2 V,
Automatic CE power
down current — CMOS VIN > VCC – 0.2 V or VIN < 0.2 V,
inputs
f = 0, VCC = 3.60 V
–
1
5
–
1
20
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max)=VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
Document Number: 001-08402 Rev. *O
Page 4 of 18
CY62136FV30 MoBL®
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, two
layer printed circuit board
75
77
C/W
10
13
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-08402 Rev. *O
Page 5 of 18
CY62136FV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR [11]
Data retention current
Conditions
VCC = 1.5 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
tCDR [12]
Chip deselect to data retention
time
tR [13]
Operation recovery time
Min
Typ [10]
Max
Unit
1.5
–
–
V
Industrial/
Automotive-A
–
–
4
A
Automotive-E
–
–
12
0
–
–
ns
ns
CY62136FV30LL-45
45
–
–
CY62136FV30LL-55
55
–
–
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
VCC
CE or
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
BHE.BLE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-08402 Rev. *O
Page 6 of 18
CY62136FV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
-45 (Industrial/Automotive-A) -55 (Automotive-E)
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
55
–
ns
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE LOW to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
tLZOE
OE LOW to low Z [17]
5
–
5
–
ns
–
18
–
20
ns
10
–
10
–
ns
–
18
–
20
ns
tHZOE
OE HIGH to high Z
tLZCE
CE LOW to low Z
[17, 18]
[17]
[17, 18]
tHZCE
CE HIGH to high Z
tPU
CE LOW to power up
0
–
0
–
ns
tPD
CE HIGH to power down
–
45
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
22
–
25
ns
5
–
5
–
ns
BLE/BHE HIGH to high Z [17, 18]
–
18
–
20
ns
tLZBE
BLE/BHE LOW to low Z
tHZBE
Write Cycle
tWC
[17]
[19, 20]
Write cycle time
45
–
55
–
ns
tSCE
CE LOW to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
35
–
40
–
ns
tSD
BLE/BHE LOW to write end
Data setup to write end
25
–
25
–
ns
tHD
Data Hold From Write End
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
[17, 18]
tHZWE
WE LOW to high Z
tLZWE
WE HIGH to low Z [17]
Notes
15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production. .
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
20. The minimum write cycle pulse width for Write Cycle No. 3 and Write Cycle No. 4 should be equal to the sum of tHZWE and tSD.
Document Number: 001-08402 Rev. *O
Page 7 of 18
CY62136FV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No.1: Address Transition Controlled [21, 22]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2: OE Controlled [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-08402 Rev. *O
Page 8 of 18
CY62136FV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No 1: WE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 27
tHD
DATAIN
tHZOE
Figure 8. Write Cycle 2: CE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 27
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *O
Page 9 of 18
CY62136FV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle 3: WE controlled, OE LOW [28, 29]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 30
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [28, 29]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 30
tSD
tHD
DATAIN
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *O
Page 10 of 18
CY62136FV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
[31]
[31]
X
X
Inputs or Outputs
Mode
Power
High Z
Deselect or power-down
Standby (ISB)
Output disabled
Active (ICC)
H
X
X
L
X
X
H
H
High Z
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
X
X
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
31. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted.
Document Number: 001-08402 Rev. *O
Page 11 of 18
CY62136FV30 MoBL®
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY62136FV30LL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
CY62136FV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
Industrial
CY62136FV30LL-45ZSXA
51-85087 44-pin TSOP II (Pb-free)
Automotive-A
CY62136FV30LL-55ZSXE
51-85087 44-pin TSOP II (Pb-free)
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 3
6
F V30 LL - XX XX X
X
Temperature Grade: X = I or A or E
I = Industrial; A = Automotive-A or E = Automotive-E
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width = × 16
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-08402 Rev. *O
Page 12 of 18
CY62136FV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-08402 Rev. *O
Page 13 of 18
CY62136FV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-08402 Rev. *O
Page 14 of 18
CY62136FV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
ns
nanosecond
TSOP
Thin Small Outline Package
%
percent
VFBGA
Very Fine-Pitch Ball Grid Array
pF
picofarad
WE
Write Enable
ohm
V
volt
W
watt
Document Number: 001-08402 Rev. *O
Symbol
Unit of Measure
Page 15 of 18
CY62136FV30 MoBL®
Document History Page
Document Title: CY62136FV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-08402
Revision
ECN
Submission
Date
Orig. of
Change
**
467351
See ECN
NXR
New data sheet.
*A
797956
See ECN
VKN
Changed status from Preliminary to Final.
Updated Features:
Changed value of Typical standby current from 0.5 A to 1.0 A.
Changed value of Maximum standby current from 2.5 A to 5.0 A.
Updated Electrical Characteristics:
Changed maximum value of ICC parameter corresponding to Test Condition
“f = 1 MHz” from 2.25 A to 2.5 A.
Changed typical value of ISB1 parameter from 0.5 A to 1.0 A.
Changed maximum value of ISB1 parameter from 2.5 A to 5.0 A.
Changed typical value of ISB2 parameter from 0.5 A to 1.0 A.
Changed maximum value of ISB2 parameter from 2.5 A to 5.0 A.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 0.5 A to 1.0 A.
Changed maximum value of ICCDR parameter from 2.5 A to 4.0 A.
*B
869500
See ECN
VKN
Added Automotive Temperature Grade related information in all instances
across the document.
Updated Switching Characteristics:
Added Note “Access time parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. Please see application note
AN3842 for further clarification.” and referred the same in tACE parameter.
Updated Ordering Information.
*C
901800
See ECN
VKN
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Updated Switching Characteristics:
Removed Note from tACE parameter and added the same note in “Parameters”
column with some updates (Replaced Access time parameters with AC
parameters in the note).
*D
1371124
See ECN
*E
2594937
10/22/08
NXR /
PYRS
Added Automotive-A Temperature Grade related information in all instances
across the document.
Updated Switching Characteristics:
Changed minimum value of tLZBE parameter corresponding to 55 ns speed bin
from 10 ns to 5 ns.
*F
2675375
03/17/2009
VKN /
PYRS
Updated Product Portfolio:
Corrected typo (Replaced A with mA for unit of Standby ISB2).
Document Number: 001-08402 Rev. *O
Description of Change
VKN / AESA Changed status of Automotive information from Preliminary to Final (Removed
shades).
Updated Electrical Characteristics:
Changed minimum value of IIX parameter corresponding to 55 ns speed bin from
–1 A to –4 A.
Changed maximum value of IIX parameter corresponding to 55 ns speed bin from
+1 A to +4 A.
Changed minimum value of IOZ parameter corresponding to 55 ns speed bin
from –1 A to –4 A.
Changed maximum value of IOZ parameter corresponding to 55 ns speed bin from
+1 A to +4 A.
Updated Switching Characteristics:
Changed maximum value of tDBE parameter corresponding to 55 ns speed bin
from 55 ns to 25 ns.
Page 16 of 18
CY62136FV30 MoBL®
Document History Page (continued)
Document Title: CY62136FV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-08402
Revision
ECN
Submission
Date
*G
2882113
02/19/2010
*H
2943752
06/03/2010
VKN
*I
3055169
10/12/2010
RAME
Updated all foot notes from table notes.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated Package Diagrams.
*J
3263825
06/17/2011
RAME
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Data Retention Characteristics (Minimum value of tR parameter).
Updated to new template.
*K
3376161
09/19/2011
RAME
No technical updates.
Completing Sunset Review.
*L
4102266
08/22/2013
VINI
Updated Switching Characteristics:
Updated Note 16.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*M
4581648
11/27/2014
VINI
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
*N
4989003
10/27/2015
NILE
Updated Switching Characteristics:
Added Note 20 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 29 and referred the same note in Figure 9 and Figure 10.
Updated Truth Table.
Updated to new template.
Completing Sunset Review.
*O
6010500
01/02/2018
Document Number: 001-08402 Rev. *O
Orig. of
Change
Description of Change
VKN / AESA Updated Truth Table:
Corrected typo.
Updated Package Diagrams.
Updated Truth Table:
Added footnote related to Chip enable and Byte enables.
Updated Package Diagrams.
AESATMP8 Updated logo and Copyright.
Page 17 of 18
CY62136FV30 MoBL®
Sales, Solutions, and Legal Information
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Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2006-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-08402 Rev. *O
Revised January 2, 2018
Page 18 of 18
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