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CY621472E30 MoBL
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE1
HIGH or CE2 LOW or both BLE and BHE are HIGH). The input
and output pins (I/O0 through I/O15) are placed in a high
impedance state when:
Very high speed: 45 ns
Temperature range
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Ultra low standby power
❐ Typical standby current: 2.5 A
❐ Maximum standby current: 7 A (Industrial)
■ Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE Features
■
■
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package
(TSOP) II package
■
Byte power down feature
■
Deselected (CE1 HIGH or CE2 LOW)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE1 LOW and CE2 HIGH and WE
LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A17). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
11 for a complete description of read and write modes.
For a complete list of related documentation, click here.
Functional Description
The CY621472E30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Logic Block Diagram
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A17
A15
A16
A13
A14
A12
BHE
BLE
CIRCUIT
A11
CE
POWER DOWN
BHE
WE
CE1
CE2
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-67798 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY621472E30 MoBL
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-67798 Rev. *G
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Page 2 of 16
CY621472E30 MoBL
Product Portfolio
Power Dissipation
Product
CY621472E30LL
Range
Industrial
VCC Range (V)
Min
Typ [1]
Max
2.2
3.0
3.6
Speed
(ns)
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2
(A)
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
3.5
6
15
20
2.5
7
Pin Configuration
Figure 1. 44-pin TSOP II pinout
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
CE2
A8
A9
A10
A11
A12
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-67798 Rev. *G
Page 3 of 16
CY621472E30 MoBL
DC input voltage [2, 3] ......... –0.3 V to 3.9 V (VCCmax + 0.3 V)
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch up current...................................................... > 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Supply voltage to ground
potential ...........................–0.3 V to +3.9 V (VCCmax + 0.3 V)
DC Voltage Applied to Outputs
in High Z State [2, 3] ............ –0.3 V to 3.9 V (VCCmax + 0.3 V)
Device
Range
Ambient
Temperature
VCC [4]
CY621472E30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
45 ns
Unit
Min
Typ [5]
Max
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
V
IOL = 2.1 mA, VCC = 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
–
15
20
mA
–
3.5
6
–
2.5
7
A
–
2.5
7
A
f = 1 MHz
ISB1 [6]
Automatic CE power-down
current – CMOS inputs
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
CE1 > VCC – 0.2 V, CE2 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
ISB2 [6]
Automatic CE Power down
current – CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
2. VIL(min) = –2.0 V for pulse durations less than 20 ns.
3. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. Chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
Document Number: 001-67798 Rev. *G
Page 4 of 16
CY621472E30 MoBL
Capacitance
Parameter [7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [7]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
44-pin TSOP II Unit
Package
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
77
C/W
13
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
INCLUDING
JIG AND
SCOPE
10%
GND
Rise Time = 1 V/ns
R2
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
Parameters
2.50 V
R1
R2
RTH
V
3.0 V
Unit
16667
1103
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-67798 Rev. *G
Page 5 of 16
CY621472E30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR[9]
Data retention current
Conditions
VCC = 1.5 V,
Min
Typ [8]
Max
Unit
1.5
–
–
V
–
3
8.8
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR [10]
Chip deselect to data retention
time
0
–
–
ns
tR [11]
Operation recovery time
45
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform [12, 13]
DATA RETENTION MODE
VCC
CE or
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
BHE.BLE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
12. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-67798 Rev. *G
Page 6 of 16
CY621472E30 MoBL
Switching Characteristics
Over the Operating Range
Parameter [14]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW/CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[15]
5
–
ns
–
18
ns
tLZOE
tHZOE
OE LOW to Low Z
OE HIGH to High Z
[15, 16]
[15]
tLZCE
CE1 LOW/CE2 HIGH to Low Z
10
–
ns
tHZCE
CE1 HIGH/CE2 LOW to High Z [15, 16]
–
18
ns
tPU
CE1 LOW/CE2 HIGH to Power-up
0
–
ns
tPD
CE1 HIGH/CE2 LOW to Power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
tLZBE
BLE/BHE LOW to Low Z [15, 17]
5
–
ns
–
18
ns
tHZBE
Write Cycle
BLE/BHE HIGH to High Z
[15, 16]
[18, 19]
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High Z [15, 16]
–
18
ns
10
–
ns
tLZWE
WE HIGH to Low Z
[15]
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. If both byte enables are together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for WRITE Cycle 4 (WE controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
Document Number: 001-67798 Rev. *G
Page 7 of 16
CY621472E30 MoBL
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
ICC
50%
ISB
Notes
20. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
21. WE is HIGH for read cycle.
22. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
23. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-67798 Rev. *G
Page 8 of 16
CY621472E30 MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 28
tHD
DATAIN
tHZOE
Figure 7. Write Cycle No. 2 (CE Controlled) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 28
tHZOE
Notes
24. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
25. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any
of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
26. Data I/O is high impedance if OE = VIH.
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-67798 Rev. *G
Page 9 of 16
CY621472E30 MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [29, 30, 31]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 32
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [29, 30]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 32
tSD
tHD
DATAIN
tLZWE
Notes
29. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
30. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
31. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
32. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-67798 Rev. *G
Page 10 of 16
CY621472E30 MoBL
Truth Table
CE1
H
CE2
I/Os
Mode
Power
WE
OE
BHE
BLE
[33]
X
X
X
X
High Z
Deselect/Power-down
Standby (ISB)
X
X[33]
L
X
X
X
X
High Z
Deselect/Power-down
Standby (ISB)
[33]
X
X
H
H
High Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
H
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
[33]
X
X
Note
33. The ‘X’ (Don’t care) state for the chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-67798 Rev. *G
Page 11 of 16
CY621472E30 MoBL
Ordering Information
Speed
(ns)
45
Ordering Code
CY621472E30LL-45ZSXI
Package
Diagram
Package Type
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 4
7 2
E 30
LL - 45
ZS
X
I
Temperature Range: I = Industrial
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 = 45 ns
Low Power
Voltage Range: 30 = 3 V Typical
Process Technology: E = 90 nm
Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-67798 Rev. *G
Page 12 of 16
CY621472E30 MoBL
Package Diagram
Figure 10. 44-pin TSOP II (18.4 × 10.2 × 1.194 mm) Package Outline, 51-85087
51-85087 *F
Document Number: 001-67798 Rev. *G
Page 13 of 16
CY621472E30 MoBL
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
OE
Output Enable
MHz
megahertz
SRAM
Static Random Access Memory
A
microampere
TSOP
Thin Small Outline Package
s
microsecond
WE
Write Enable
mA
milliampere
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-67798 Rev. *G
Symbol
Unit of Measure
Page 14 of 16
CY621472E30 MoBL
Document History Page
Document Title: CY621472E30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 001-67798
Rev.
ECN No.
Submission
Date
**
3184883
03/01/2011
New data sheet.
*A
3223503
04/15/2011
Updated Truth Table:
Removed overline bar for CE2 in column heading.
Updated to new template.
*B
3261142
05/19/2011
Updated Switching Characteristics:
Changed minimum value of tLZBE parameter from 10 ns to 5 ns.
Added Ordering Information and Ordering Code Definitions.
Added Acronyms and Units of Measure.
*C
3365953
09/08/2011
Changed status from Preliminary to Final.
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *D.
*D
3414567
10/20/2011
Replaced CY62147EV30 with CY621472E30 in all instances across the document.
*E
4331825
04/03/2014
Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 31 and referred the same note in Figure 8.
Updated Package Diagram:
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*F
4573121
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*G
6906316
06/26/2020
Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to
“f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 0.8 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagram:
spec 51-85087 – Changed revision from *E to *F.
Updated to new template.
Document Number: 001-67798 Rev. *G
Description of Change
Page 15 of 16
CY621472E30 MoBL
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