CY62147CV18

CY62147CV18 MoBL2™ 256K x 16 Static RAM Features • High speed — 55 ns and 70 ns availability • Low voltage range: — 1.65V−1.95V • Pin-compatible w/ CY62147BV18 • Ultra-low active power — Typical Active Current: 0.5 mA @ f = 1 MHz • • • • — Typical Active Current: 2 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The CY62147CV18 is available in a 48-ball FBGA package. Functional Description The CY62147CV18 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Logic Block Diagram DATA IN DRIVERS A10 A9 ROW DECODER SENSE AMPS A8 A7 A6 A5 A4 A3 A2 A1 A0 256K x 16 RAM Array 2048 X 2048 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE CE BHE BLE A11 A12 A13 A14 Power-down Circuit Cypress Semiconductor Corporation Document #: 38-05011 Rev. *C • 3901 North First Street A15 A16 A17 • San Jose • CA 95134 • 408-943-2600 Revised August 28, 2002 CY62147CV18 MoBL2™ Pin Configuration[1, 2] 1 FBGA Top View BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 3 A0 A3 A5 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vccq Vssq I/O6 I/O7 NC A B C D E F G H I/O11 A17 I/O12 DNU I/O13 NC A8 A14 A12 A9 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.2V to +2.4V DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.2V to VCC + 0.2V DC Input Voltage[3] ................................ –0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC CY62147CV18 Industrial −40°C to +85°C 1.65V to 1.95V Product Portfolio Power Dissipation (Industrial) Operating (ICC) VCC Range Product CY62147CV18 VCC(min.) VCC(typ.)[4] 1.65V 1.80V VCC(max.) 1.95V Speed 55 ns 70 ns f = 1 MHz Typ.[4] 0.5 mA 0.5 mA Max. 3 mA 3 mA f = fmax Typ.[4] 2.5 mA 2 mA Max. 7 mA 6 mA Standby (ISB2) Typ.[4] 1 µA Max. 10 µA Electrical Characteristics Over the Operating Range CY62147CV18-55 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V 1.4 –0.2 –1 Min. 1.4 0.2 VCC + 0.2V 0.4 +1 1.4 –0.2 –1 Typ.[4] Max. CY62147CV18-70 Min. 1.4 0.2 VCC + 0.2V 0.4 +1 Typ.[4] Max. Unit V V V V µA Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or VSS to ensure proper application. 3. VIL(min) = −2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ) Typ, TA = 25°C. Document #: 38-05011 Rev. *C Page 2 of 11 CY62147CV18 MoBL2™ Electrical Characteristics Over the Operating Range (continued) CY62147CV18-55 Parameter IOZ ICC Description Output Leakage Current VCC Operating Supply Current Test Conditions GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 1.95V IOUT = 0 mA CMOS levels Min. –1 2.5 0.5 1 Typ.[4] Max. +1 7 3 10 CY62147CV18-70 Min. –1 2 0.5 1 Typ.[4] Max. Unit +1 6 3 10 µA mA mA µA ISB1 Automatic CE CE > VCC − 0.2V, VIN > VCC − 0.2V, Power-down Current— VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE, CMOS Inputs and BLE) Automatic CE CE > VCC − 0.2V VIN > VCC − 0.2V Power-down Current— or VIN < 0.2V, f = 0, VCC = 1.95V CMOS Inputs ISB2 Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF Thermal Resistance Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board BGA 55 16 Unit °C/W °C/W AC Test Loads and Waveforms R1 VCC OUTPUT GND 30 pF INCLUDING JIG AND SCOPE R2 Rise Time: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH ALL INPUT PULSES VCC Typ 10% 90% 90% 10% Fall Time: 1 V/ns OUTPUT V Parameters R1 R2 RTH VTH 1.8V 13500 10800 6000 0.80 Unit Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.0V, CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V Conditions Min. 1.0 1 Typ.[4] Max. 1.95 8 Unit V µA Note: 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05011 Rev. *C Page 3 of 11 CY62147CV18 MoBL2™ Data Retention Characteristics (Over the Operating Range) (continued) Parameter tCDR[5] tR[6] Description Chip Deselect to Data Retention Time Operation Recovery Time Conditions Min. 0 tRC Typ.[4] Max. Unit ns ns Data Retention VCC CE or BHE,BHE Waveform[7] DATA RETENTION MODE VCC(min.) tCDR VDR > 1.0 V VCC(min.) tR Switching Characteristics Over the Operating Range Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[11] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9, 10] WE HIGH to Low-Z[9] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to CE LOW to Low-Z[9] Low-Z[9] Description [8] 55 ns Min. 55 55 10 55 25 5 20 5 20 0 55 55 5 20 55 40 40 0 0 40 40 25 0 15 5 10 70 60 60 0 0 50 60 30 0 5 0 10 5 10 Max. Min. 70 70 ns Max. Unit ns 70 70 35 25 25 70 70 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 ns ns OE HIGH to High-Z[9, 10] CE HIGH to High-Z[9, 10] CE LOW to Power-up CE HIGH to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low-Z[9] BLE/BHE HIGH to High-Z[9, 10] Notes: 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 8. Test conditions assume signal transition time of 3ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05011 Rev. *C Page 4 of 11 CY62147CV18 MoBL2™ Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS CE tACE OE tRC tPD tHZCE BHE/BLE tDOE tHZOE tLZOE tDBE tLZBE tHZBE HIGH IMPEDANCE DATA VALID DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 12. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW. Document #: 38-05011 Rev. *C Page 5 of 11 CY62147CV18 MoBL2™ Switching Waveforms Write Cycle No. 1(WE Controlled) [11, 15, 16] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD Write Cycle No. 2 (CE Controlled) [11, 15, 16] tWC ADDRESS tSCE CE tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05011 Rev. *C Page 6 of 11 CY62147CV18 MoBL2™ Switching Waveforms Write Cycle No. 3 (WE Controlled, OE LOW) [16] tWC ADDRESS tSCE CE BHE/BLE tAW tSA WE tBW tHA tPWE tSD DATA I/O NOTE 17 tHZWE DATAIN VALID tHD tLZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [16] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 17 DATAIN VALID tHD tBW tHA Document #: 38-05011 Rev. *C Page 7 of 11 CY62147CV18 MoBL2™ Typical DC and AC Characteristics (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C.) Operating Current vs. Supply Voltage MoBL2 2.4 ICC (mA) ISB (µA) 2.0 1.6 1.2 0.8 0.4 0.0 1.65 1.80 SUPPLY VOLTAGE (V) (f = 1 MHz) (f = fmax, 70 ns) (f = fmax, 55 ns) Standby Current vs. Supply Voltage 3.5 3.0 2.0 1.5 1.0 0.5 0 1.95 1.65 1.80 1.95 SUPPLY VOLTAGE (V) MoBL2 Access Time vs. Supply Voltage 40 35 30 TAA (ns) 25 20 15 10 1.65 1.8 SUPPLY VOLTAGE (V) 1.95 MoBL2 Truth Table CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High-Z High-Z Data Out (I/OO–I/O15) Data Out (I/OO–I/O7); I/O8–I/O15 in High-Z Data Out (I/O8–I/O15); I/O0–I/O7 in High-Z High-Z High-Z High-Z Data In (I/OO–I/O15) Data In (I/OO–I/O7); I/O8–I/O15 in High-Z Data In (I/O8–I/O15); I/O0 –I/O7 in High-Z Mode Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05011 Rev. *C Page 8 of 11 CY62147CV18 MoBL2™ Ordering Information Speed (ns) 70 55 Ordering Code CY62147CV18LL-70BAI CY62147CV18LL-70BVI CY62147CV18LL-55BAI CY62147CV18LL-55BVI Package Name BA48B BV48A BA48B BV48A Package Type 48-ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B 51-8 510 6-*C Document #: 38-05011 Rev. *C Page 9 of 11 CY62147CV18 MoBL2™ Package Diagrams (continued) 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05011 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62147CV18 MoBL2™ Document Title: CY62147CV18 MoBL2™ 256K x 16 Static RAM Document Number: 38-05011 REV. ** *A *B ECN NO. 106265 108941 110573 Issue Date 5/7/01 08/24/01 11/02/01 Orig. of Change HRT/MGN New Data Sheet MGN MGN From Preliminary to Final Improved ISB Typ. from 1.5 µA to 1 µA. Improved Typical DC and AC Characteristics graphs. Improved Switching Characteristics: tOHA, tLZCE. Added preliminary package diagram of BV48A. Format standardization Removed Preliminary status for BV package Description of Change *C 115864 09/04/02 MGN Document #: 38-05011 Rev. *C Page 11 of 11