CY62147EV18LL-45BVXIT

CY62147EV18 MoBL2™ 4-Mbit (256K x 16) Static RAM Features also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). • Very high speed: 45 ns • Wide voltage range: 1.65V–2.25V • Pin-compatible with CY62147DV18 • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 7 µA • Ultra-low active power Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). — Typical active current: 2 mA @ f = 1 MHz • Ultra low standby power • Easy memory expansion with CE, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. • Available in a 48-ball Pb-free VFBGA package Functional Description[1] The CY62147EV18 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device The CY62147EV18 is available in a 48-ball VFBGA package. Logic Block Diagram SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 BHE WE CE OE BLE A17 A13 A14 A15 A16 A11 A12 COLUMN DECODER CE Power-down Circuit BHE BLE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05441 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 12, 2005 CY62147EV18 MoBL2™ Pin Configuration[2, 3] 48-ball VFBGA Pinout Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 NC A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Product Portfolio Power Dissipation Product CY62147EV18-45LL VCC Range (V) [4] Min. Typ. Max. 1.65 1.8 2.25 Speed (ns) Operating ICC (mA) f = 1MHz [4] Typ. 45 2 Max. 2.5 f = fmax Typ. [4] 15 Standby ISB2 (µA) Max. Typ.[4] Max. 20 1 7 Notes: 2. NC pins are not connected on the die. 3. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05441 Rev. *B Page 2 of 11 CY62147EV18 MoBL2™ DC Input Voltage[5,6] ........... –0.2V to 2.45V (VCCMAX + 0.2V) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ..........................–0.2V to + 2.45V (VCCMAX + 0.2V) DC Voltage Applied to Outputs in High-Z State[5,6] ...............–0.2V to 2.45V (VCCMAX + 0.2V) Device Ambient Temperature Range VCC [7] CY62147EV18 Industrial –40°C to +85°C 1.65V to 2.25V Electrical Characteristics (Over the Operating Range) 45 ns Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V Min. Typ.[4] Max. Unit 0.2 V 1.4 V VIH Input HIGH Voltage VCC =1.65V to 2.25V 1.4 VCC+ 0.2V V VIL Input LOW Voltage VCC =1.65V to 2.25V –0.2 0.4 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply f = fMAX = 1/tRC Current VCC(max)=2.25V IOUT = 0 mA CMOS levels 15 20 mA VCC(max)=2.25V 2 2.5 mA VCC(max)=2.25V CE > VCC−0.2V, VIN>VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) VCC(max)=2.25V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 1 7 µA 1 7 µA f = 1 MHz ISB1 Automatic CE Power-down Current — CMOS Inputs ISB2 Automatic CE Power-down Current — CMOS Inputs Capacitance (for all Packages) [8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. Unit 10 pF 10 pF Note: 5. VIL(min.) = –2.0V for pulse durations less than 20 ns. 6. VIH(max)=VCC+0.5V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05441 Rev. *B Page 3 of 11 CY62147EV18 MoBL2™ Thermal Resistance Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient)[8] ΘJC Thermal Resistance (Junction to Case)[8] Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board VFBGA Package Unit 75 °C/W 10 °C/W AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF 10% GND Rise Time = 1 V/ns R2 INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalentto: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 1.80V Unit R1 13500 Ω R2 10800 Ω RTH 6000 Ω VTH 0.80 V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[7] Chip Deselect to Data Retention Time tR[9] Operation Recovery Time Min. Typ.[4] Max. 1.0 Unit V 0.5 VCC= 1.0V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 3 µA 0 ns tRC ns Data Retention Waveform[10] VCC CE or BHE.BLE VCC(min) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min) tR Notes: 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100µs. 10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05441 Rev. *B Page 4 of 11 CY62147EV18 MoBL2™ Switching Characteristics (Over the Operating Range) [11] 45 ns Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change 45 tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to LOW Z [12] 10 [12] CE HIGH to High ns 22 ns ns 10 CE LOW to Low Z tHZCE ns 18 OE HIGH to High Z tLZCE Z[12, 13] ns 45 5 [12, 13] tHZOE ns 45 ns ns 18 0 ns ns tPU CE LOW to Power-up tPD CE HIGH to Power-down 45 ns BLE/BHE LOW to Data Valid 45 ns tDBE tLZBE BLE/BHE LOW to Low tHZBE Write Z[12 ] BLE/BHE HIGH to HIGH 10 Z[12, 13] ns 18 ns Cycle[14] tWC Write Cycle Time 45 tSCE CE LOW to Write End Address Set-up to Write End 35 ns tAW 35 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 35 ns ns tSD BLE/BHE LOW to Write End Data Set-up to Write End 35 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High-Z[12, 13] tBW tLZWE WE HIGH to Low-Z[12] ns 18 10 ns ns Notes: 11. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state 14. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05441 Rev. *B Page 5 of 11 CY62147EV18 MoBL2™ Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[16, 17] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 15. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE and BHE, BLE transition LOW. Document #: 38-05441 Rev. *B Page 6 of 11 CY62147EV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[14, 18, 19] tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O NOTE 20 tHD DATAIN tHZOE Write Cycle No. 2 (CE Controlled)[14, 18, 19] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 20 tHZOE Notes: 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 20. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05441 Rev. *B Page 7 of 11 CY62147EV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[19] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O NOTE 20 tHD DATAIN tLZWE tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 20 tSD tHD DATAIN tLZWE Document #: 38-05441 Rev. *B Page 8 of 11 CY62147EV18 MoBL2™ Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-down Standby (ISB) L X X H H High Z Deselect/Power-down Standby (ISB) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type CY62147EV18LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array Pb-Free Operating Range Industrial Please contact your local Cypress sales representative for availability of other parts Document #: 38-05441 Rev. *B Page 9 of 11 CY62147EV18 MoBL2™ Package Diagram 48-pin VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER 2 3 4 5 6 6 4 5 3 2 1 A B C C E F G D E F 2.625 8.00±0.10 D 0.75 A B 5.25 8.00±0.10 1 Ø0.30±0.05(48X) G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 51-85150-*D C 1.00 MAX 0.26 MAX. SEATING PLANE MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05441 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62147EV18 MoBL2™ Document History Page Document Title:CY62147EV18 MoBL2™ 4-Mbit (256K x 16) Static RAM Document Number: 38-05441 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201580 01/08/04 AJU New Data Sheet *A 247009 See ECN SYT Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCCMax from 2.20 to 2.25 V Changed VCC stabilization time in footnote #8 from 100 µs to 200 µs Removed Footnote #15 (tLZBE) from Previous Revision Changed ICCDR from 2.0 µA to 2.5 µA Changed typo in Data Retention Characteristics (tR) from 100 µs to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages *B 414820 See ECN ZSD Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62147EV18 Changed ball E3 from DNU to NC Changed ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Max) value from 2 mA to 2.5 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f=fmax Changed ISB1 and ISB2 Typ. values from 0.7 µA to 1 µA and Max. values from 2.5 µA to 7 µA. Extended undershoot limit to -2V in footnote #5 Changed ICCDR Max. from 2.5 µA to 3 µA. Added ICCDR typical value. Changed tLZOE from 3 ns to 5 ns Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns. Changed tSD from 22 ns to 25 ns. Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering information table and replaced Package Name column with Package Diagram Document #: 38-05441 Rev. *B Page 11 of 11