CY62147EV18LL-55BVXIT

CY62147EV18 MoBL® 4-Mbit (256 K × 16) Static RAM 4-Mbit (256 K × 16) Static RAM is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both the Byte High Enable and the Byte Low Enable are disabled (BHE, BLE HIGH), or during an active write operation (CE LOW and WE LOW). Features ■ Very high speed: 55 ns ■ Wide voltage range: 1.65 V to 2.25 V ■ Pin compatible with CY62147DV18 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Ultra low standby power ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in a Pb-free 48-ball very fine ball grid array (VFBGA) package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins apears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes. Functional Description The CY62147EV18 is a high performance CMOS static RAM organized as 256 K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This For a complete list of related documentation, click here. Logic Block Diagram ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SENSE AMPS DATA IN DRIVERS 256K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 COLUMN DECODER Cypress Semiconductor Corporation Document Number: 38-05441 Rev. *L • A17 A15 198 Champion Court A16 A13 A14 BLE A11 BHE A12 CE POWER DOWN CIRCUIT • BHE WE CE OE BLE San Jose, CA 95134-1709 • 408-943-2600 Revised November 23, 2015 CY62147EV18 MoBL® Contents Product Portfolio .............................................................. 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05441 Rev. *L Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY62147EV18 MoBL® Product Portfolio Power Dissipation VCC Range (V) Product CY62147EV18LL Operating ICC (mA) Speed (ns) Min Typ [1] Max 1.65 1.8 2.25 f = 1MHz Standby ISB2 (A) f = fmax Typ [1] Max Typ [1] Max Typ [1] Max 2 2.5 15 20 1 7 55 Pin Configuration Figure 1. 48-ball VFBGA pinout [2, 3] Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 2. NC pins are not connected on the die. 3. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively. Document Number: 38-05441 Rev. *L Page 3 of 17 CY62147EV18 MoBL® Maximum Ratings DC input voltage [4, 5] ....... –0.2 V to 2.45 V (VCCmax + 0.2 V) Exceeding the maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Output current into outputs (LOW) ............................. 20 mA Ambient temperature with power applied ......................................... –55 °C to + 125 °C Latch up current ..................................................... > 200 mA Supply voltage to ground potential [4, 5] .................–0.2 V to + 2.45 V (VCCmax + 0.2 V) Operating Range DC voltage applied to outputs in High Z state [4, 5] ........... –0.2 V to 2.45 V (VCCmax + 0.2 V) Static discharge voltage (MIL-STD-883, Method 3015) ................................ > 2001 V Device Range Ambient Temperature VCC[6] CY62147EV18LL Industrial –40 °C to +85 °C 1.65 V to 2.25 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 55 ns Unit Min Typ [7] Max 1.4 – – V – 0.2 V V VOH Output high voltage IOH = –0.1 mA VOL Output low voltage IOL = 0.1 mA VIH Input high voltage VCC = 1.65 V to 2.25 V 1.4 – VCC + 0.2 VIL Input low voltage VCC = 1.65 V to 2.25 V –0.2 – 0.4 V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VO < VCC, Output Disabled –1 – +1 A ICC VCC operating supply current f = fmax = 1/tRC VCC(max) = 2.25 V IOUT = 0 mA CMOS levels – 15 20 mA f = 1 MHz VCC(max) = 2.25 V – 2 2.5 mA ISB1[8] VCC(max) = 2.25 V Automatic power down current – CE > VCC – 0.2 V or CMOS inputs (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE, and WE), VCC = VCC (max) – 1 7 A ISB2[8] VCC(max) = 2.25 V Automatic power down current – CE > VCC  0.2 V or CMOS inputs (BHE and BLE) > VCC – 0.2 V, VIN > VCC  0.2 V or VIN < 0.2 V, f = 0, VCC = VCC (max) – 1 7 A Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) =VCC+0.5 V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05441 Rev. *L Page 4 of 17 CY62147EV18 MoBL® Capacitance Parameter [9] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 10 pF 10 pF Test Conditions VFBGA Package Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 54 C/W 12 C/W TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [9] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF R2 INCLUDING JIG AND SCOPE 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 1.80V Unit R1 13500  R2 10800  RTH 6000  VTH 0.80 V Note 9. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05441 Rev. *L Page 5 of 17 CY62147EV18 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for data retention ICCDR[11] Data retention current tCDR[12] Chip deselect to data retention time tR[13] Operation recovery time VCC = 1.0 V, CE > VCC – 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Typ [10] Max Unit 1.0 – – V – 0.5 5 A 0 – – ns 55 – – ns Data Retention Waveform Figure 3. Data Retention Waveform [14] DATA RETENTION MODE VCC CE or VCC(min) tCDR VDR > 1.0 V VCC(min) tR BHE.BLE Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document Number: 38-05441 Rev. *L Page 6 of 17 CY62147EV18 MoBL® Switching Characteristics Over the Operating Range Parameter [15,16] Description 55 ns Unit Min Max 55 – ns – 55 ns 10 – ns 55 ns 25 ns Read Cycle tRC Read cycle time tAA Address to data valid tOHA Data hold from address change tACE tDOE CE LOW to data valid OE LOW to data valid – tLZOE OE LOW to Low Z [17] 5 – ns – 18 ns 10 – ns – 18 ns tHZOE tLZCE OE HIGH to High Z CE LOW to Low Z [17, 18] [17] [17, 18] tHZCE CE HIGH to High Z tPU CE LOW to power up 0 – ns tPD CE HIGH to power down BLE/BHE LOW to data valid – 55 ns – 55 ns 10 – ns – 18 ns Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA ns tDBE tLZBE tHZBE Write Cycle tWC BLE/BHE LOW to Low Z [17] BLE/BHE HIGH to High Z [17, 18] [19, 20] Address setup to write start 0 – tPWE WE pulse width 35 – ns tBW 35 – ns tSD BLE/BHE LOW to write end Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns [17, 18] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z [17] Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5 section 16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in production. 17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedence state 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 20. The minimum pulse width for write cycle 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05441 Rev. *L Page 7 of 17 CY62147EV18 MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [21, 22] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [22, 23] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 21. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 22. WE is high for read cycle. 23. Address valid before or similar to CE and BHE, BLE transition low. Document Number: 38-05441 Rev. *L Page 8 of 17 CY62147EV18 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled) [24, 25, 26] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD NOTE 27 tHD DATAIN tHZOE Figure 7. Write Cycle No. 2 ( CE Controlled) [24, 25, 26] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 27 tHZOE Notes 24. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. 25. Data I/O is high impedance if OE = VIH. 26. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05441 Rev. *L Page 9 of 17 CY62147EV18 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled and OE LOW) [28] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA I/O NOTE 29 tHD DATAIN tLZWE tHZWE Figure 9. Write Cycle No. 4 (BHE/BLE Controlled and OE LOW) [28] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 29 tSD tHD DATAIN tLZWE Notes 28. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 29. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05441 Rev. *L Page 10 of 17 CY62147EV18 MoBL® Truth Table CE WE OE BHE BLE H X X X[30] X[30] X X H H L H L L L H L L H L Inputs or Outputs X[30] High-Z Mode Power Deselect or power down Standby (ISB) High-Z Deselect or power down Standby (ISB) L Data out (I/O0 – I/O15) Read Active (ICC) H L Data out (I/O0 – I/O7); I/O8–I/O15 in High-Z Read Active (ICC) L L H Data out (I/O8–I/O15); I/O0–I/O7 in High-Z Read Active (ICC) H H L L High-Z Output disabled Active (ICC) L H H H L High-Z Output disabled Active (ICC) L H H L H High-Z Output disabled Active (ICC) L L X L L Data in (I/O0–I/O15) Write Active (ICC) L L X H L Data in (I/O0–I/O7); I/O8–I/O15 in High-Z Write Active (ICC) L L X L H Data in (I/O8–I/O15); I/O0–I/O7 in High-Z Write Active (ICC) Note 30. The ‘X’ (Do not care) state for the Chip enable (CE) and byte enables (BHE and BLE) in the truth table refer to the logic state (either high or low). Intermediate voltage levels on this pin is not permitted. Document Number: 38-05441 Rev. *L Page 11 of 17 CY62147EV18 MoBL® Ordering Information Speed (ns) 55 Package Diagram Ordering Code CY62147EV18LL-55BVXI Package Type 51-85150 48-ball VFBGA (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of other parts. Ordering Code Definitions CY 621 4 7 E V18 LL 55 BVX I Temperature grade: I = Industrial Package type: BVX: VFBGA (Pb-free) Speed grade Low power Voltage range = 1.8 V typical E = Process Technology 90 nm Bus width = x16 Density = 4 Mbit 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05441 Rev. *L Page 12 of 17 CY62147EV18 MoBL® Package Diagram Figure 10. 48-Ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05441 Rev. *L Page 13 of 17 CY62147EV18 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz CE Chip Enable A microampere I/O Input/Output mA milliampere OE Output Enable ns nanosecond SRAM Static Random Access Memory  ohm TSOP Thin Small Outline Package pF picofarad VFBGA Very Fine-Pitch Ball Grid Array V volt WE Write Enable W watt Document Number: 38-05441 Rev. *L Symbol Unit of Measure Page 14 of 17 CY62147EV18 MoBL® Document History Page Document Title: CY62147EV18 MoBL®, 4-Mbit (256 K × 16) Static RAM Document Number: 38-05441 Rev. ECN No. Submission Date Orig. of Change ** 201580 01/08/04 AJU New data sheet. *A 247009 See ECN SYT Changed status from Advance Information to Preliminary. Moved Product Portfolio to Page 2 Changed VCCMax from 2.20 to 2.25 V Changed VCC stabilization time in footnote #8 from 100 s to 200 s Removed Footnote #15 (tLZBE) from Previous Revision Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages *B 414820 See ECN ZSD Changed status from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35 ns Speed Bin Removed “L” version of CY62147EV18 Changed ball E3 from DNU to NC Changed ICC(typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC(max) value from 2 mA to 2.5 mA at f = 1 MHz Changed ICC(typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A Extended undershoot limit to –2 V in footnote #5 Changed ICCDR Max from 2.5 A to 3 A Added ICCDR typical value Changed tLZOE from 3 ns to 5 ns Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 22 ns to 25 ns Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering information table and replaced Package Name Column with Package Diagram *C 571786 See ECN VKN Replaced 45ns speed bin with 55 ns Document Number: 38-05441 Rev. *L Description of Change Page 15 of 17 CY62147EV18 MoBL® Document History Page (continued) Document Title: CY62147EV18 MoBL®, 4-Mbit (256 K × 16) Static RAM Document Number: 38-05441 Rev. ECN No. Submission Date Orig. of Change *D 908120 See ECN VKN Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters Changed tWC specification from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns Changed tHZWE specification from 18 ns to 20 ns *E 1045701 See ECN VKN Changed ICCDR specification from 3 A to 5 A *F 1274728 See ECN VKN / AESA *G 2944332 06/04/2010 VKN Added Contents Added footnote related to chip enable in Truth Table Updated Package Diagram. Added Sales, Solutions, and Legal Information. *H 3047228 10/06/2010 RAME Updated and converted all table notes into footnotes. Updated Electrical Characteristics. Updated Data Retention Characteristics. Updated Package Diagram: spec 51-85150 – Changed revision from *E to *F. Added Acronyms and Units of Measure. *I 3302815 07/29/2011 RAME Removed AN1064 reference from the document. Updated Ordering Code Definition. Updated to new template. *J 4102266 08/22/2013 VINI Updated Switching Characteristics: Updated Note 16. Updated Package Diagram: spec 51-85150 – Changed revision from *F to *H. Updated to new template. Completing Sunset Review. *K 4574264 11/19/2014 VINI Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Maximum Ratings: Referred Notes 4 and 5 in “Supply voltage to ground potential”. Updated Switching Characteristics: Added Note 20 and referred the same note in “Write Cycle”. *L 5023825 11/23/2015 VINI Updated Thermal Resistance: Changed value of JA parameter corresponding to VFBGA Package from 75 C/W to 54 C/W. Changed value of JC parameter corresponding to VFBGA Package from 10 C/W to 12 C/W. Updated to new template. Completing Sunset Review. Document Number: 38-05441 Rev. *L Description of Change Changed tWC specification from 55 ns to 45 ns Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns Changed tHZWE specification from 20 ns to 18 ns Page 16 of 17 CY62147EV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05441 Rev. *L Revised November 23, 2015 Page 17 of 17 MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.