CY62148CV30

CY62148CV25/30/33 MoBL™ 512K x 8 MoBL Static RAM Features • High Speed — 55 ns and 70 ns availability • Low voltage range: — CY62148CV25: 2.2V–2.7V — CY62148CV30: 2.7V–3.3V — CY62148CV33: 3.0V–3.6V • Pin compatible with CY62148V • Ultra low active power — Typical active current: 1.5 mA @ f = 1MHz • • • • — Typical active current: 5.5 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can be put into standby mode when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). The CY62148CV25/30/33 are available in a 36-ball FBGA package. Functional Description The CY62148CV25/30/33 are high-performance CMOS static RAMs organized as 512K words by 8 bits. This device features Logic Block Diagram Data in Drivers I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 512K x 8 ARRAY CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 Cypress Semiconductor Corporation Document #: 38-05035 Rev. *A • 3901 North First Street A10 A 11 A 12 A13 A14 A15 A16 A17 A18 • San Jose • CA 95134 • 408-943-2600 Revised September 7, 2001 CY62148CV25/30/33 MoBL™ Pin Configurations[1,2] 1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 OE A10 A18 CE A11 A17 A16 A12 A15 A13 2 A1 A2 FBGA (Top View) 3 NC WE DNU 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14 A B C D E F G H Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .... .............................–65°C to +150°C Ambient Temperature with Power Applied. ............................................–55°C to +125°C Supply Voltage to Ground Potential.....–0.5V to Vccmax + 0.5V DC Voltage Applied to Outputs in High Z State[3] ...................................–0.5V to VCC + 0.3V DC Input Voltage[3] ................................–0.5V to VCC + 0.3V Output Current into Outputs (LOW).. ...........................20 mA Static Discharge Voltage..........................................>2001V MIL-STD-883, Method 3015) Latch-Up Current >...................................................>200 mA Operating Range Product CY62148CV25 CY62148CV30 CY62148CV33 Range Industrial Ambient Temperature –40°C to +85°C VCC 2.2V to 2.7V 2.7V to 3.3V 3.0V to 3.6V Product Portfolio Power Dissipation (Industrial) Operating (ICC) VCC Range Product CY62148CV25 CY62148CV30 CY62148CV33 Min. 2.2V 2.7V 3.0V Typ.[4] 2.5V 3.0V 3.3V Max. 2.7V 3.3V 3.6V Speed 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns f = 1 MHz Typ.[4] 1.5 mA 1.5 mA 1.5 mA 1.5 mA 1.5 mA 1.5 mA Max. 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA f = fmax Typ.[4] 7 mA 5.5 mA 7 mA 5.5 mA 7 mA 5.5 mA Max. 15 mA 12 mA 15 mA 12 mA 15 mA 12 mA 8 µA 20 µA 7 µA 15 µA Typ.[4] 5 µA Max. 15 µA Standby (ISB2) Notes: 1. NC pins are not connected to the die. 2. C3 (DNU) can be left as NC or Vss to ensure proper application. 3. VIL(min.) = –2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05035 Rev. *A Page 2 of 13 CY62148CV25/30/33 MoBL™ Electrical Characteristics Over the Operating Range CY62148CV25-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — CMOS Inputs Automatic CE Power-Down Current — CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V IOUT = 0 mA CMOS Levels Test Conditions IOH = –0.1 mA IOL = 0.1 mA VCC = Min. VCC = MinV 1.8 –0.3 –1 –1 7 1.5 5 Min. 2.0 0.4 VCC+ 0.3V 0.6 +1 +1 15 3 15 1.8 –0.3 –1 –1 5.5 1.5 5 Typ. [4] CY62148CV25-70 Min. Typ.[4] 2.0 0.4 VCC + 0.3V 0.6 +1 +1 12 3 15 Max. Unit V V V V µA µA mA mA µA Max. ISB1 CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE,WE) CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V ISB2 CY62148CV30-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — CMOS Inputs Automatic CE Power-Down Current — CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V IOUT = 0 mA CMOS Levels Test Conditions IOH = –1.0 mA IOL = 2.1 mA VCC = Min. VCC = MinV 2.2 –0.3 –1 –1 12 1.5 7 Min. 2.4 0.4 VCC+ 0.5V 0.8 +1 +1 25 3 15 Typ.[4] Max. CY62148CV30-70 Min. Typ.[4] 2.4 0.4 2.2 –0.3 –1 –1 7 1.5 7 VCC + 0.5V 0.8 +1 +1 15 3 15 Max. Unit V V V V µA µA mA mA µA ISB1 CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE,WE) CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V ISB2 Document #: 38-05035 Rev. *A Page 3 of 13 CY62148CV25/30/33 MoBL™ CY62148CV33-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — CMOS Inputs Automatic CE Power-Down Current — CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V IOUT = 0 mA CMOS Levels Test Conditions IOH = –1.0 mA IOL = 2.1 mA VCC = 3.0V VCC = 3.0V 2.2 –0.3 –1 –1 7 1.5 8 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 3 20 Typ.[4] Max. CY62148CV33-70 Min. 2.4 0.4 2.2 –0.3 –1 –1 5.5 1.5 8 VCC+ 0.5V 0.8 +1 +1 12 3 20 Typ.[4] Max. Unit V V V V µA µA mA mA µA ISB1 CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE,WE) CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V ISB2 Capacitance[5 Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance[5] (Junction to Ambient) Thermal Resistance[5] (Junction to Case) Note: 5. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board Symbol ΘJA ΘJC BGA 55 16 Unit °C/W °C/W Document #: 38-05035 Rev. *A Page 4 of 13 CY62148CV25/30/33 MoBL™ AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC Typ 10% GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall time: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH VTH OUTPUT Parameters R1 R2 RTH VTH 2.5V 16.6 15.4 8.0 1.20 3.0V 1.105 1.550 0.645 1.75 3.3V 1.216 1.374 0.645 1.75 Unit K Ohms K Ohms K Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.5V CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 3 Typ.[4] Max. Vccmax 10 Unit V µA ns ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min.) tCDR CE VDR > 1.5V VCC(min.) tR Note: 6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. Document #: 38-05035 Rev. *A Page 5 of 13 CY62148CV25/30/33 MoBL™ Switching Characteristics Over the Operating Range[7] 55 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [10, 11] 70 ns Max. Min. 70 55 70 10 55 25 70 35 5 20 25 10 20 25 0 55 70 70 60 60 0 0 50 30 0 20 25 10 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[8] OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z [9] [8] [8, 9] Min. 55 10 5 10 0 CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [8, 9] 55 45 45 0 0 45 30 0 5 WE HIGH to Low Z[8] Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05035 Rev. *A Page 6 of 13 CY62148CV25/30/33 MoBL™ Switching Waveforms Read Cycle No. 1 [12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 [13, 14] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tRC tHZOE tHZCE DATA VALID tPD HIGH IMPEDANCE DATA OUT ICC 50% ISB Write Cycle No. 1 (WE Controlled) [10, 15, 16] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. tHD DATAIN VALID Document #: 38-05035 Rev. *A Page 7 of 13 CY62148CV25/30/33 MoBL™ Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [10, 15, 16] tWC ADDRESS CE tSA tAW WE tSD DATA I/O [11, 16] tSCE tHA tHD DATAIN VALID Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O NOTE 17 tHZWE DATAIN VALID tHD tLZWE Document #: 38-05035 Rev. *A Page 8 of 13 CY62148CV25/30/33 MoBL™ Typical DC and AC Parameters (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.) Operating Current vs. Supply Voltage 14.0 12.0 ICC (mA) 10.0 8.0 6.0 4.0 2.0 (f = 1 MHz) (f = fmax, 55ns) (f = fmax, 70ns) MoBL ICC (mA) 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) (f = 1 MHz) (f = fmax, 55ns) (f = fmax, 70ns) MoBL ICC (mA) 14.0 12.0 10.0 8.0 6.0 4.0 (f = 1 MHz) 0.0 3.3 3.0 3.6 SUPPLY VOLTAGE (V) 2.0 (f = fmax, 55ns) (f = fmax, 70ns) MoBL 0.0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) Standby Current vs. Supply Voltage 12.0 ISB (µA) ISB (µA) 10.0 8.0 6.0 4.0 2.0 0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) MoBL 12.0 MoBL ISB (µA) 10.0 8.0 6.0 4.0 2.0 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 12.0 MoBL 10.0 8.0 6.0 4.0 2.0 0 3.0 3.3 3.6 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage MoBL 60 50 40 TAA (ns) TAA (ns) 30 20 10 0 2.2 2.5 2.7 60 50 40 TAA (ns) 30 20 10 0 2.7 3.0 3.3 MoBL 60 50 40 30 20 10 0 3.0 3.3 3.6 MoBL SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05035 Rev. *A Page 9 of 13 CY62148CV25/30/33 MoBL™ Ordering Information Speed (ns) 70 Ordering Code CY62148CV25LL-70BAI CY62148CV25LL-70BVI CY62148CV30LL-70BAI CY62148CV30LL-70BVI CY62148CV33LL-70BAI CY62148CV33LL-70BVI 55 CY62148CV25LL-55BAI CY62148CV25LL-55BVI CY62148CV30LL-55BAI CY62148CV30LL-55BVI CY62148CV33LL-55BAI CY62148CV33LL-55BVI Package Name BA36B BV36A BA36B BV36A BA36B BV36A BA36B BV36A BA36B BV36A BA36B BV36A Package Type 36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) 36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial Document #: 38-05035 Rev. *A Page 10 of 13 CY62148CV25/30/33 MoBL™ Package Diagrams 36-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA36B 51-85105-*C Document #: 38-05035 Rev. *A Page 11 of 13 CY62148CV25/30/33 MoBL™ Package Diagrams (continued) 36-Lead VFBGA (6 x 8 x 1 mm) BV36A 51-85149-** MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05035 Rev. *A Page 12 of 13 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62148CV25/30/33 MoBL™ Document Title: CY62148CV25/30/33 MoBL™ 512K x 8 MoBL Static RAM Document Number: 38-05035 REV. ** *A ECN NO. 109951 110643 Issue Date 12/02/01 05/01/02 Orig. of Change SZV MGN Description of Change Change from Spec number: 38-01126 to 38-05035 Advance to Final, Improved Typical and Max Icc values, added BV package Document #: 38-05035 Rev. *A Page 13 of 13