CY62148ESL-55ZAXIT

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62148ESL MoBL 4-Mbit (512K × 8) Static RAM 4-Mbit (512K × 8) Static RAM Features Functional Description ■ Higher speed up to 55 ns The CY62148ESL is a high performance CMOS static RAM organized as 512K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications. The device also has an automatic power-down feature that significantly reduces power consumption. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). ■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical standby current: 2.5 µA ❐ Maximum standby current: 7 µA ■ Ultra low active power ❐ Typical active current: 3.5 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 32-pin shrunk thin small outline package (STSOP) package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The CY62148ESL device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related resources, click here. Logic Block Diagram I/O00 IO INPUT BUFFER I/O1 IO 1 512K x 8 ARRAY I/O3 IO 3 I/O4 IO 4 I/O5 IO 5 I/O6 IO 6 CE • I/O IO77 POWER DOWN A17 A18 A15 A13 A14 OE A16 COLUMN DECODER WE Cypress Semiconductor Corporation Document Number: 001-50045 Rev. *K I/O2 IO 2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 26, 2020 CY62148ESL MoBL Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 001-50045 Rev. *K Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY62148ESL MoBL Pin Configuration Figure 1. 32-pin STSOP (Top View) pinout A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Product Portfolio Power Dissipation Product CY62148ESL Range VCC Range (V) [1] Industrial/ 2.2 V to 3.6 V and 4.5 V to 5.5 V Automotive-A Speed (ns) 55 Operating ICC, (mA) f = 1 MHz f = fmax Standby, ISB2 (µA) Typ [2] Max Typ [2] Max Typ [2] Max 3.5 6 15 20 2.5 7 Notes 1. Data sheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 001-50045 Rev. *K Page 3 of 17 CY62148ESL MoBL Maximum Ratings Output current into outputs (low) .................................20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ... 55 °C to +125 °C Supply voltage to ground potential ................ –0.5 V to 6.0 V DC voltage applied to outputs in high Z state [3, 4] ........................................ –0.5 V to 6.0 V Static discharge voltage (MIL-STD-883, Method 3015) .................................> 2001 V Latch-up current .....................................................> 200 mA Operating Range Device CY62148ESL DC input voltage [3, 4] .................................... –0.5 V to 6.0 V Range Ambient Temperature VCC[5] Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V, Automotive-A and 4.5 V to 5.5 V Electrical Characteristics Over the operating range Parameter VOH VOL VIH VIL [8] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 55 ns (Industrial/Automotive-A) Min Typ [6] Max 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – 2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – – 4.5 < VCC < 5.5 IOH = –1.0 mA 2.4 – – 4.5 < VCC < 5.5 IOH = –0.1 mA – – 3.4 [7] 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 2.7 < VCC < 3.6 IOL = 2.1 mA – – 0.4 4.5 < VCC < 5.5 IOL = 2.1 mA – – 0.4 2.2 < VCC < 2.7 1.8 – VCC + 0.3 2.7 < VCC < 3.6 2.2 – VCC + 0.3 4.5 < VCC < 5.5 2.2 – VCC + 0.5 2.2 < VCC < 2.7 –0.3 – 0.4 2.7 < VCC < 3.6 –0.3 – 0.6 4.5 < VCC < 5.5 –0.5 – 0.6 Unit V V V V IIX Input leakage current GND < VIN < VCC –1 – +1 µA IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 µA ICC VCC operating supply current f = fmax = 1/tRC – 15 20 mA – 3.5 6 2.5 7 µA 2.5 7 µA f = 1 MHz ISB1[9] ISB2[9] VCC = VCCmax IOUT = 0 mA, CMOS levels Automatic CE power-down current – CMOS inputs CE > VCC –0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE and WE), VCC = VCC(max) – Automatic CE power-down current – CMOS inputs CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max) – – – Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 6. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider 8. Under DC conditions the device meets a VIL of 0.8 V (for VCC range of 2.7 V to 3.6 V and 4.5 V to 5.5 V) and 0.6 V (for VCC range of 2.2 V to 2.7 V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6 V and 0.4 V for the above ranges. 9. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating. Document Number: 001-50045 Rev. *K Page 4 of 17 CY62148ESL MoBL Capacitance Parameter [10] Description CIN Input capacitance COUT Output capacitance Test Conditions Max TA = 25 °C, f = 1 MHz, VCC = VCC(Typ) Unit 10 pF 10 pF Thermal Resistance Parameter [10] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 32-pin STSOP Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 49.02 C/W 14.07 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC R2 30 pF INCLUDING JIG AND SCOPE GND Rise Time = 1 V/ns Equivalent to: 2.5 V R1 R2 RTH 8000 VTH 1.20 Fall Time = 1 V/ns THEVENIN EQUIVALENT OUTPUT Parameter 90% 10% 90% 10% RTH VTH 3.0 V 5.0 V Unit 16667 1103 1800  15385 1554 990  645 639  1.75 1.77 V Note 10. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-50045 Rev. *K Page 5 of 17 CY62148ESL MoBL Data Retention Characteristics Over the operating range Parameter VDR ICCDR Description Conditions VCC for data retention [12] Data retention current CE > VCC – 0.2 V, Industrial / VIN > VCC – 0.2 V or Automotive-A VIN < 0.2 V, VCC = 1.5 V Min Typ [11] Max Unit 1.5 – – V – 3 8.8 µA tCDR Chip deselect to data retention time 0 – – ns tR [13] Operation recovery time 55 – – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 12. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document Number: 001-50045 Rev. *K Page 6 of 17 CY62148ESL MoBL Switching Characteristics Over the operating range Parameter [14, 15] Description 55 ns (Industrial / Automotive-A) Min Unit Max Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to low Z [16] 5 – ns – 20 ns 10 – ns tHZOE tLZCE OE HIGH to high Z CE LOW to low Z [16, 17] [16] [16, 17] tHZCE CE HIGH to high Z – 20 ns tPU CE LOW to power-up 0 – ns CE HIGH to power-up – 55 ns tPD Write Cycle [18, 19] tWC Write cycle time 55 – ns tSCE CE LOW to write end 40 – ns tAW Address setup to write end 40 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 40 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 20 ns 10 – ns [16, 17] tHZWE WE LOW to high Z tLZWE WE HIGH to low Z [16] Notes 14. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Notes is no longer applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production. 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5. 16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 19. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 001-50045 Rev. *K Page 7 of 17 CY62148ESL MoBL Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21] tRC RC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATAOUT VALID Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE HIGH IMPEDANCE DATA I/O VCC SUPPLY CURRENT tLZCE tHZCE HIGH IMPEDANCE DATAOUT VALID tPD tPU 50% 50% ICC ISB Notes 20. Device is continuously selected. OE, CE = VIL. 21. WE is HIGH for read cycles. 22. Address valid before or similar to CE transition LOW. 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-50045 Rev. *K Page 8 of 17 CY62148ESL MoBL Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [26, 27] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATAIN VALID Figure 7. Write Cycle No. 2 (WE Controlled) [27] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 28 tHD DATAIN VALID tHZWE tLZWE Notes 26. Data I/O is high impedance if OE = VIH. 27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-50045 Rev. *K Page 9 of 17 CY62148ESL MoBL Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [29, 30] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 31 tHD DATA VALID tHZWE tLZWE Notes 29. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 30. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. 31. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-50045 Rev. *K Page 10 of 17 CY62148ESL MoBL Truth Table CE H WE OE [32] I/O Mode Power X X High Z Deselect/power-down Standby (ISB) L H L Data out Read Active (ICC) L H H High Z Output disabled Active (ICC) L L X Data in Write Active (ICC) Note 32. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 001-50045 Rev. *K Page 11 of 17 CY62148ESL MoBL Ordering Information Table 1 lists the CY62148ESL MoBL key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Key features and Ordering Information Speed (ns) 55 Ordering Code Package Diagram Package Type Operating Range CY62148ESL-55ZAXI 51-85094 32-pin STSOP (Pb-free) Industrial CY62148ESL-55ZAXA 51-85094 32-pin STSOP (Pb-free) Automotive-A Ordering Code Definitions CY 621 4 8 E SL - 55 ZA X X Temperature Grade: X = I or A I = Industrial; A = Automotive-A Pb-free Package Type: ZA = 32-pin STSOP Speed Grade: 55 ns SL = Wide Voltage Range (3 V Typical; 5 V Typical) Process Technology: E = 90 nm Bus width: 8 = × 8 Density: 4 = 4-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 001-50045 Rev. *K Page 12 of 17 CY62148ESL MoBL Package Diagram Figure 9. 32-pin STSOP (8 × 13.4 × 1.2 mm) ZA32 Package Outline, 51-85094 51-85094 *G Document Number: 001-50045 Rev. *K Page 13 of 17 CY62148ESL MoBL Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output mA milliampere OE Output Enable ns nanosecond SRAM Static Random Access Memory  ohm TSOP Thin Small Outline Package pF picofarad WE Write Enable V volt W watt Document Number: 001-50045 Rev. *K Symbol Unit of Measure Page 14 of 17 CY62148ESL MoBL Document History Page Document Title: CY62148ESL MoBL, 4-Mbit (512K × 8) Static RAM Document Number: 001-50045 Rev. ECN Submission Date Description of Change ** 2612938 01/21/2009 New data sheet. *A 2800124 11/06/2009 Updated Product Portfolio (Included Automotive-A information). Updated Operating Range (Included Automotive-A information). Updated Ordering Information: Updated part numbers. *B 2947039 06/10/2010 Updated Electrical Characteristics: Added Note 9 and referred the same note in ISB2 parameter. Updated Truth Table: Added Note 32 and referred the same note in “CE” column. Updated Package Diagram: spec 51-85094 – Changed revision from *D to *E. *C 3006318 08/23/2010 Updated Electrical Characteristics: Updated Note 9 and referred the same note in ISB1 parameter. Updated Data Retention Characteristics: Added Note 12 and referred the same note in ICCDR parameter. Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated to new template. *D 3296704 06/29/2011 Updated Functional Description: Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.” at the end. Updated Ordering Information: No change in part numbers. Updated Ordering Code Definitions. Updated Package Diagram: spec 51-85094 – Changed revision from *E to *F. *E 3515577 02/03/2012 Updated Switching Waveforms: Updated Figure 4. Updated Figure 5. Updated Figure 6. Updated Figure 7. Updated Figure 8. Completing Sunset Review. *F 3548240 03/12/2012 Updated Electrical Characteristics: Updated Note 8 (Removed “Refer to AN13470 for details.”). *G 3897076 02/06/2013 Updated Switching Waveforms: Removed figure “Write Cycle No. 1 (WE Controlled, OE HIGH During Write)”. Updated Figure 7 (Updated caption only). Completing Sunset Review. *H 4039358 07/01/2013 Updated Functional Description: Updated description. Updated Electrical Characteristics: Added one more Test Condition “4.5 < VCC < 5.5” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 7 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “4.5 < VCC < 5.5”. Updated to new template. *I 4099182 08/19/2013 Updated Switching Characteristics: Added Note 14 and referred the same note in “Parameter” column. Document Number: 001-50045 Rev. *K Page 15 of 17 CY62148ESL MoBL Document History Page (continued) Document Title: CY62148ESL MoBL, 4-Mbit (512K × 8) Static RAM Document Number: 001-50045 Rev. ECN Submission Date *J 4779516 05/28/2015 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated AC Test Loads and Waveforms: Updated Figure 2. Updated Switching Characteristics: Added Note 19 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Figure 8. Added Note 29, 30, 31 and referred the same note in Figure 8. Updated Package Diagram: spec 51-85094 – Changed revision from *F to *G. Updated to new template. *K 6906316 06/26/2020 Updated Features: Changed value of Typical standby current from 1 µA to 2.5 µA. Changed value of Typical active current from 2 mA to 3.5 mA. Updated Product Portfolio: Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to “f = 1 MHz”. Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to “f = 1 MHz”. Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA. Updated Electrical Characteristics: Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to Test Condition “f = 1 MHz”. Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to Test Condition “f = 1 MHz”. Changed typical value of ISB1 parameter from 1 µA to 2.5 µA. Changed typical value of ISB2 parameter from 1 µA to 2.5 µA. Updated Data Retention Characteristics: Changed typical value of ICCDR parameter from 1 μA to 3 μA. Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA. Updated to new template. Document Number: 001-50045 Rev. *K Description of Change Page 16 of 17 CY62148ESL MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-50045 Rev. *K Revised June 26, 2020 MoBL is the registered trademark, and More Battery Life is the trademark of Cypress Semiconductor Corporation. Page 17 of 17