CY62148VNLL-70ZSXIT

CY62148VN MoBL® 4 Mbit (512K x 8) Static RAM Features applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can be put into standby mode when deselected (CE HIGH). ■ Wide Voltage Range: 2.7V to 3.6V ■ Ultra Low Active Power ■ Low Standby Power ■ TTL-compatible Inputs and Outputs ■ Automatic Power Down when deselected ■ CMOS for optimum Speed and Power ■ Package available in a 32-Pin TSOP II and a 32-Pin SOIC Package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Functional Description The CY62148VN is a high performance CMOS static RAM organized as 512K words by eight bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram I/O0 Data in Drivers I/O1 512K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A10 A 11 A 12 A13 A14 A15 A16 A17 A18 WE OE Cypress Semiconductor Corporation Document #: 001-55636 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 09, 2009 [+] Feedback CY62148VN MoBL® Pin Configuration Figure 1. 32-Pin TSOP II/SOIC (Top View) A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 4 32 31 30 29 5 6 28 27 7 8 9 10 11 12 26 25 1 2 3 24 23 22 21 20 19 18 17 13 14 15 16 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 Product Portfolio Power Dissipation VCC Range (V) Product Min Typ[1] Max Speed (ns) CY62148VNLL 2.7 3.0 3.6 70 Operating ICC, (mA) Standby ISB2, (μA) Typ[1] Max Typ[1] Max 7 15 2 20 Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 001-55636 Rev. ** Page 2 of 11 [+] Feedback CY62148VN MoBL® DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .............................................. 55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Supply Voltage to Ground Potential................–0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2].................................... –0.5V to VCC + 0.5V Range Ambient Temperature VCC Industrial –40°C to +85°C 2.7V to 3.6V Electrical Characteristics Over the Operating Range CY62148VN-70 Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage VCC = 3.6V VIL Input LOW Voltage VCC = 2.7V IIX Input Load Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current IOUT = 0 mA, f = 1 MHz CMOS Levels ISB1 Automatic CE Power down Current— CMOS Inputs CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f = fMAX ISB2 Automatic CE Power down Current— CMOS Inputs CE > VCC − 0.3V VIN > VCC − 0.3V or VIN < 0.3V, f = 0 GND < VI < VCC IOUT = 0 mA, f = fMAX = 1/tRC CMOS Levels Min. Typ.[1] Max. Unit 2.4 V 0.4 V 2.2 VCC + 0.5V V –0.5 0.8 V –1 +1 +1 μA –1 +1 +1 μA 7 15 mA 1 2 mA 2 20 μA VCC = 3.6V VCC = 3.6V Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.0V Max Unit 6 pF 8 pF TSOP II SOIC Unit TBD TBD °C/W TBD TBD °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, four-layer printed circuit board Note 2. VIL(min.) = –2.0V for pulse durations less than 20 ns. Document #: 001-55636 Rev. ** Page 3 of 11 [+] Feedback CY62148VN MoBL® Figure 2. AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC TYP OUTPUT 10% R2 50 pF INCLUDING JIG AND SCOPE GND Rise time: 1V/ns Equivalent to: 90% 10% Fall time: 1V/ns THÉVENIN EQUIVALENT OUTPUT Parameters 90% 3.0V Unit R1 1105 Ω R2 1550 Ω RTH 645 Ω VTH 1.75V V Rth Vth Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[4] Operation Recovery Time Min. Typ.[1] 1.0 VCC = 1.0V, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V; No input may exceed VCC + 0.3V 0.2 Max. Unit 3.6 V 5.5 μA 0 ns tRC ns Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 1.0V VDR > 1.0 V tCDR 1.0V tR CE Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 μs or stable at VCC(min.) > 10 μs. Document #: 001-55636 Rev. ** Page 4 of 11 [+] Feedback CY62148VN MoBL® Switching Characteristics Over the Operating Range[5] Parameter Description 70 ns Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns tLZOE OE LOW to Low 70 Z[6] 70 10 tHZOE OE HIGH to High CE LOW and to Low Z[6] tHZCE CE HIGH to High tPU CE1 LOW and CE2 HIGH to Power Up tPD CE1 HIGH and CE2 LOW to Power Down ns 25 10 Z[6, 7] ns ns 5 Z[7] tLZCE ns ns ns 25 0 ns ns 70 ns Write Cycle[8, 9] tWC Write Cycle Time 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 60 ns tAW Address Setup to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 50 ns tSD Data Setup to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High Z[6, 7] WE HIGH to Low Z[6] 25 10 ns ns Notes 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-55636 Rev. ** Page 5 of 11 [+] Feedback CY62148VN MoBL® Switching Waveforms Figure 4. Read Cycle No. 1: Address Transition Controlled [10, 11] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [11, 12] tRC CE tACE OE DATA OUT tHZOE tHZCE tDOE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Figure 6. Write Cycle No 1: WE Controlled [8, 13, 14] tWC ADDRESS CE tAW tSA WE tHA tPWE OE tSD DATA I/O NOTE 15 tHD DATAIN VALID tHZOE Notes 10. The device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid before or similar to CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. Document #: 001-55636 Rev. ** Page 6 of 11 [+] Feedback CY62148VN MoBL® Switching Waveforms (continued) Figure 7. Write Cycle 2: CE Controlled [8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAIN VALID Figure 8. Write Cycle 3: WE controlled, OE LOW [14] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O NOTE 15 tHZWE tHD DATAIN VALID tLZWE Note 15. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-55636 Rev. ** Page 7 of 11 [+] Feedback CY62148VN MoBL® Typical DC and AC Characteristics 1.4 Standby Current vs. Supply Voltage 45 Normalized Operating Current vs. Supply Voltage 40 1.2 35 ISB (μA) ICC 1.0 0.8 0.6 30 25 20 0.4 15 0.2 0.0 1.7 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 10 1.0 3.7 2.8 1.9 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 80 70 60 TAA (ns) 50 40 30 20 10 1.0 2.8 1.9 SUPPLY VOLTAGE (V) 3.7 Truth Table CE WE OE Inputs/Outputs Mode Power H X X High-Z Deselect/Power down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High-Z Output Disabled Active (ICC) Ordering Information Speed (ns) 70 Ordering Code Package Name Package Type CY62148VNLL-70ZSXI 51-85095 32-Pin TSOP II CY62148VNLL-70SXI 51-85081 32-Pin (450-mil) Molded SOIC Document #: 001-55636 Rev. ** Operating Range Industrial Page 8 of 11 [+] Feedback CY62148VN MoBL® Package Diagrams Figure 9. 32-Pin (450-mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] DIMENSIONS IN INCHES[MM] MIN. MAX. PACKAGE WEIGHT 1.42gms S32.45 SZ32.45 0.440[11.176] 0.450[11.430] 17 PART # STANDARD PKG. LEAD FREE PKG. 32 0.006[0.152] 0.012[0.304] 0.793[20.142] 0.817[20.751] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.047[1.193] 0.063[1.600] 0.004[0.102] 0.004[0.102] MIN. 0.050[1.270] BSC. 0.023[0.584] 0.039[0.990] 51-85081 *C 0.014[0.355] 0.020[0.508] SEATING PLANE Document #: 001-55636 Rev. ** Page 9 of 11 [+] Feedback CY62148VN MoBL® Package Diagrams (continued) Figure 10. 32-Pin TSOP II, 51-85095 51-85095 ** Document #: 001-55636 Rev. ** Page 10 of 11 [+] Feedback CY62148VN MoBL® Document History Page Document Title: CY62148VN MoBL®, 4 Mbit (512K x 8) Static RAM Document Number: 001-55636 Rev. ECN No. Orig. of Change ** 2761558 VKN Submission Date Description of Change 09/09/2009 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-55636 Rev. ** Revised September 09, 2009 Page 11 of 11 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback