CY62148VNLL

CY62148VN MoBL® 4 Mbit (512K x 8) Static RAM Features ■ ■ ■ ■ ■ ■ ■ Wide Voltage Range: 2.7V to 3.6V Ultra Low Active Power Low Standby Power TTL-compatible Inputs and Outputs Automatic Power Down when deselected CMOS for optimum Speed and Power Package available in a 32-Pin TSOP II and a 32-Pin SOIC Package applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can be put into standby mode when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Functional Description The CY62148VN is a high performance CMOS static RAM organized as 512K words by eight bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable Logic Block Diagram Data in Drivers I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 512K x 8 ARRAY CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A10 A 11 A 12 A13 A14 A15 A16 A17 A18 Cypress Semiconductor Corporation Document Number : 001-55636 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 6, 2010 [+] [+] Feedback CY62148VN MoBL® Pin Configuration Figure 1. 32-Pin TSOP II/SOIC (Top View) A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 Product Portfolio Power Dissipation VCC Range (V) Product CY62148VNLL Min 2.7 Typ[1] 3.0 Max 3.6 Speed (ns) 70 Operating ICC, (mA) Typ[1] 7 Max 15 2 Standby ISB2, (A) Typ[1] Max 20 Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document Number : 001-55636 Rev. *A Page 2 of 10 [+] [+] Feedback CY62148VN MoBL® Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .............................................. 55°C to +125°C Supply Voltage to Ground Potential................–0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2].................................... –0.5V to VCC + 0.5V DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40°C to +85°C VCC 2.7V to 3.6V Electrical Characteristics Over the Operating Range CY62148VN-70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current VCC Operating Supply Current Automatic CE Power down Current— CMOS Inputs Automatic CE Power down Current— CMOS Inputs GND < VI < VCC IOUT = 0 mA, f = fMAX = 1/tRC CMOS Levels VCC = 3.6V Output Leakage Current GND < VO < VCC, Output Disabled IOH = –1.0 mA IOL = 2.1 mA Test Conditions VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 –0.5 –1 –1 +1 +1 7 1 2 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 2 20 Typ.[1] Max. Unit V V V V A A mA mA A IOUT = 0 mA, f = 1 MHz CMOS Levels ISB1 ISB2 CE > VCC  0.3V, VIN > VCC 0.3V or VIN < 0.3V, f = fMAX CE > VCC 0.3V VIN > VCC 0.3V or VIN < 0.3V, f = 0 VCC = 3.6V Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.0V Max 6 8 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, four-layer printed circuit board TSOP II TBD TBD SOIC TBD TBD Unit C/W C/W Note 2. VIL(min.) = –2.0V for pulse durations less than 20 ns. Document Number : 001-55636 Rev. *A Page 3 of 10 [+] [+] Feedback CY62148VN MoBL® Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC TYP GND Rise time: 1V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall time: 1V/ns Equivalent to: THÉVENIN EQUIVALENT Rth Vth OUTPUT Parameters R1 R2 RTH VTH Over the Operating Range Parameter VDR ICCDR tCDR[3] tR[4] 3.0V 1105 1550 645 1.75V Unit    V Data Retention Characteristics Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Figure 3. Data Retention Waveform DATA RETENTION MODE VCC CE 1.0V tCDR VDR > 1.0 V 1.0V tR Conditions VCC = 1.0V, CE > VCC 0.3V, VIN > VCC 0.3V or VIN < 0.3V; No input may exceed VCC + 0.3V Min. 1.0 Typ.[1] 0.2 Max. 3.6 5.5 Unit V A ns ns 0 tRC Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 s or stable at VCC(min.) > 10 s. Document Number : 001-55636 Rev. *A Page 4 of 10 [+] [+] Feedback CY62148VN MoBL® Switching Characteristics Over the Operating Range[5] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[8, 9] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High WE HIGH to Low Z[6, 7] Z[6] 10 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] Z[7] 10 25 0 70 Z[6, 7] 5 25 OE HIGH to High CE HIGH to High 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description 70 ns Min Max Unit CE LOW and to Low Z[6] CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down Notes 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number : 001-55636 Rev. *A Page 5 of 10 [+] [+] Feedback CY62148VN MoBL® Switching Waveforms Figure 4. Read Cycle No. 1: Address Transition Controlled [10, 11] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [11, 12] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ICC ISB tRC DATA OUT HIGH IMPEDANCE Figure 6. Write Cycle No 1: WE Controlled [8, 13, 14] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID tHD Notes 10. The device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid before or similar to CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. Document Number : 001-55636 Rev. *A Page 6 of 10 [+] [+] Feedback CY62148VN MoBL® Switching Waveforms (continued) Figure 7. Write Cycle 2: CE Controlled [8, 13, 14] tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAIN VALID tHD tHA tSCE Figure 8. Write Cycle 3: WE controlled, OE LOW [14] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O NOTE 15 tHZWE DATAIN VALID tHD tLZWE Note 15. During this period, the I/Os are in output state. Do not apply input signals. Document Number : 001-55636 Rev. *A Page 7 of 10 [+] Feedback CY62148VN MoBL® Typical DC and AC Characteristics 1.4 1.2 1.0 ISB (A) ICC 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 45 40 35 30 25 20 15 10 1.0 3.7 2.8 1.9 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 1.0 2.8 1.9 SUPPLY VOLTAGE (V) 3.7 Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Output Disabled Mode Deselect/Power down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 70 Ordering Code CY62148VNLL-70ZSXI Package Name 51-85095 32-Pin TSOP II Package Type Operating Range Industrial Document Number : 001-55636 Rev. *A Page 8 of 10 [+] [+] Feedback CY62148VN MoBL® Package Diagrams Figure 9. 32-Pin TSOP II, 51-85095 51-85095 *A Document Number : 001-55636 Rev. *A Page 9 of 10 [+] [+] Feedback CY62148VN MoBL® Document History Page Document Title: CY62148VN MoBL®, 4 Mbit (512K x 8) Static RAM Document Number: 001-55636 Rev. ** *A ECN No. 2761558 2905443 Orig. of Change VKN VKN Submission Date 09/09/2009 New data sheet 06/04/2010 Removed inactive part CY62148VNLL-70SXI from ordering information. Updated Package Diagrams. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com © Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number : 001-55636 Rev. *A Revised April 6, 2010 Page 10 of 10 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] [+] Feedback