CY62157CV18LL-70BAI

CY62157CV18 MoBL2™ 512K x 16 Static RAM Features • High Speed — 55 ns and 70 ns availability • Low voltage range: — CY62157CV18: 1.65V–1.95V • Ultra-low active power — Typical Active Current: 0.5 mA @ f = 1 MHz • • • • — Typical Active Current: 4 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected CMOS for optimum speed/power The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes. The CY62157CV18 is available in a 48-ball FBGA package. Functional Description The CY62157CV18 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 512K x 16 RAM Array 2048 X 4096 SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE OE BLE CE2 CE1 Pow er Down Circuit BHE BLE CE2 CE1 MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-05012 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 31, 2001 CY62157CV18 MoBL2™ Pin Configuration[1, 2] FBGA 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 Top View 4 3 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vccq Vssq I/O6 I/O7 NC A B C D E F G H I/O12 DNU I/O13 NC A8 A14 A12 A9 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.2V to +2.4V DC Voltage Applied to Outputs in High Z State[3 .............................................]–0.2V to VCC + 0.2V DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Operating Range Device CY62157CV18 Range Industrial Ambient Temperature –40°C to +85°C VCC 1.65V to 1.95V Product Portfolio Power Dissipation (Industrial) Operating (ICC) VCC Range Product CY62157CV18 Min. 1.65V Typ.[4] 1.8V Max. 1.95V Speed 55 ns 70 ns f = 1 MHz Typ.[4] 0.5 mA 0.5 mA Max. 3 mA 3 mA f = fmax Typ.[4] 5 mA 4 mA Max. 15 mA 12 mA Standby (ISB2) Typ.[4] 1.5 µA Max. 20 µA Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or VSS to ensure proper application. 3. VIL(min.) = –2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05012 Rev. *C Page 2 of 11 CY62157CV18 MoBL2™ Electrical Characteristics Over the Operating Range CY62157CV18-55 Parameter VOH VOL VIH VIL IIX IOZ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 1.95V IOUT = 0 mA CMOS levels Test Conditions IOH = –0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V 1.4 –0.2 –1 –1 5 0.5 1.5 Min. Typ. 1.4 0.2 VCC +0.2V 0.4 +1 +1 15 3 20 1.4 –0.2 –1 –1 4 0.5 1.5 [4] CY62157CV18-70 Min. Typ.[4] 1.4 0.2 VCC +0.2V 0.4 +1 +1 12 3 20 Max. Unit V V V V µA µA mA mA µA Max. ICC ISB1 Automatic CE CE1 > VCC − 0.2V, CE2< 0.2V Power-Down Current— VIN > VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), CMOS Inputs f = 0 (OE, WE, BHE, and BLE) Automatic CE CE1 > VCC – 0.2V or CE2 < 0.2V, Power-Down Current— VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 1.95V CMOS Inputs ISB2 Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Note: 5. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol ΘJA ΘJC BGA 55 16 Unit °C/W °C/W Document #: 38-05012 Rev. *C Page 3 of 11 CY62157CV18 MoBL2™ AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC Typ 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH V OUTPUT Parameters R1 R2 RTH VTH 1.8V 13500 10800 6000 0.80 Unit Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.0V CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.0 1 Typ.[4] Max. 1.95 10 Unit V µA tCDR[5] tR[6] Chip Deselect to Data Retention Time Operation Recovery Time ns ns Data Retention Waveform[7] DATA RETENTION MODE VCC CE1 or BHE,BLE VCC, min. tCDR VDR > 1.0 V VCC, min. tR or CE2 Notes: 6. Full Device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us or stable at VCC(min.) > 100 µs. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05012 Rev. *C Page 4 of 11 CY62157CV18 MoBL2™ Switching Characteristics Over the Operating Range[8] 55 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [11] 70 ns Max. Min. 70 55 70 10 55 25 70 35 5 20 25 10 20 25 0 55 55 70 70 5 20 25 70 60 60 0 0 50 60 30 0 20 25 10 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[9] OE HIGH to High Z [9, 10] [9] [9, 10] Min. 55 10 5 10 0 CE1 LOW and CE2 HIGH to Low Z CE1 HIGH and CE2 LOW to High Z CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH and CE2 LOW to Power-Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z [9] 5 BLE / BHE HIGH to HIGH Z[9, 10] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [9, 10] 55 45 45 0 0 45 45 25 0 5 WE HIGH to Low Z[9] Notes: 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05012 Rev. *C Page 5 of 11 CY62157CV18 MoBL2™ Switching Waveforms Read Cycle No. 1 (Address Transition controlled)[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE controlled)[13, 14] ADDRESS tRC CE1 CE2 tACE tPD tHZCE BHE/BLE tDBE tLZBE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZBE tHZOE HIGH IMPEDANCE DATA VALID ICC 50% ISB Notes: 12. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05012 Rev. *C Page 6 of 11 CY62157CV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 1(WE Controlled) [11, 15, 16] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD Write Cycle No. 2 (CE1 or CE2 Controlled) ADDRESS [11, 15, 16] tWC tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA I/O NOTE 17 tHZOE Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. tHD DATAIN VALID Document #: 38-05012 Rev. *C Page 7 of 11 CY62157CV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [16] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tAW tSA WE tBW tHA tPWE tSD DATA I/O NOTE 17 tHZWE DATAIN VALID tHD tLZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [16] tWC ADDRESS CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 17 DATAIN VALID tHD tBW tHA Document #: 38-05012 Rev. *C Page 8 of 11 CY62157CV18 MoBL2™ Typical DC and AC Characteristics (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C) Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 3.0 MoBL2 6.0 MoBL2 ICC (mA) 5.0 4.0 3.0 (f = fmax, 55 ns) ISB (µA) (f = fmax, 70 ns) 2.5 2.0 1.5 1.0 2.0 0.5 1.0 (f = 1 MHz) 0.0 1.65 1.80 SUPPLY VOLTAGE (V) 1.95 0 1.65 1.80 1.95 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 40 35 30 TAA (ns) 25 20 15 10 1.65 1.80 SUPPLY VOLTAGE (V) 1.95 MoBL2 Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data Out (I/O8–I/O15) High Z High Z High Z Data In Data In High Z High Z Data In (I/O0–I/O15) (I/O0–I/O7); (I/O8–I/O15) (I/O0–I/O7); (I/O8–I/O15) Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05012 Rev. *C Page 9 of 11 CY62157CV18 MoBL2™ Ordering Information Speed (ns) 55 70 Ordering Code CY62157CV18LL-55BAI CY62157CV18LL-70BAI Package Name BA48F Package Type 48-Ball Fine Pitch BGA Operating Range Industrial Package Diagram 48-Ball (6 mm x 10 mm x 1.2 mm) Fine Pitch BGA BA48F 51-85128-*A Document #: 38-05012 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62157CV18 MoBL2™ Document Title:CY62157CV18 MoBL2™ 512K x 16 Static RAM Document Number: 38-05012 REV. ** *A *B *C ECN NO. 106158 107242 109231 110574 Issue Date 04/06/01 07/31/01 08/31/01 11/02/01 Orig. of Change MGN MGN MGN MGN Description of Change New Data Sheet, replaces CY62157BV18. Changing from Preliminary to Final. Add comment on front page about Active Current at different frequencies. Improved tDOE from 35 ns to 25 ns (@55 ns). Added Typical DC & AC Characteristics. Format standardization Document #: 38-05012 Rev. *C Page 11 of 11