CY62157CV33LL-70BAXA

CY62157CV30/33 512K x 16 Static RAM Features significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). • Temperature Ranges — Automotive-A: –40°C to 85°C — Automotive-E: –40°C to 125°C • Voltage range: — CY62157CV30: 2.7V–3.3V — CY62157CV33: 3.0V–3.6V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz — Typical active current: 5.5 mA @ f = fmax • Low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball FBGA package Functional Description[1] The CY62157CV30/33 are high-performance CMOS static RAMs organized as 512K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that Logic Block Diagram Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62157CV30/33 are available in a 48-ball FBGA package. 512K × 16 RAM Array SENSE AMPS DATA IN DRIVERS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Writing to the device is accomplished by taking Chip Enable 1 (CE1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE CE2 CE1 OE BLE Power -down Circuit BHE BLE CE2 CE1 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05014 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 31, 2006 [+] Feedback CY62157CV30/33 Product Portfolio Power Dissipation Operating (ICC) mA VCC Range f = 1 MHz f = fmax Standby (ISB2) µA Product Range Min. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. CY62157CV30 Automotive-E 2.7V 3.0V 3.3V 1.5 3 7 15 8 70 Automotive-A 3.0V 3.3V 3.6V 1.5 3 5.5 12 10 30 1.5 3 7 15 10 80 CY62157CV33 Automotive-E Pin Configurations[2, 3, 4] FBGA (Top View) 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 DNU A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Pin Definitions Name Definition Input A0-A18. Address Inputs Input/Output I/O0-I/O15. Data lines. Used as input or output lines depending on operation Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Input/Control CE1. Chip Enable 1, Active LOW. Input/Control CE2. Chip Enable 2, Active HIGH. Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins Ground Vss. Ground for the device Power Supply Vcc. Power supply for the device Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 3. NC pins are not connected on the die. 4. E3 (DNU) can be left as NC or VSS to ensure proper application. Document #: 38-05014 Rev. *F Page 2 of 13 [+] Feedback CY62157CV30/33 Maximum Ratings Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current ................................................... > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ...–0.5V to Vccmax + 0.5V DC Voltage Applied to Outputs in High-Z State[5] ....................................–0.5V to VCC + 0.3V Device Ambient Temperature [TA][6] Range VCC CY62157CV30 Automotive-E –40°C to +125°C 2.7V – 3.3V CY62157CV33 Automotive-A –40°C to +85°C 3.0V – 3.6V DC Input Voltage[5] .................................–0.5V to VCC + 0.3V Automotive-E –40°C to +125°C Output Current into Outputs (LOW) .............................20 mA Electrical Characteristics Over the Operating Range CY62157CV30-70 Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VOL Output LOW Voltage VCC = 2.7V VIH Input HIGH Voltage IOL = 2.1 mA Typ.[2] Max. 2.4 Unit V 2.2 0.4 V VCC + 0.3V V VIL Input LOW Voltage –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –10 +10 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –10 +10 µA ICC VCC Operating Supply Current f = fMAX = 1/tRC 7 15 mA 1.5 3 ISB1 Automatic CE Power-Down Current— CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, WE, BHE and BLE) 8 70 µA ISB2 Automatic CE Power-Down Current—CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.3V 8 70 µA f = 1 MHz VCC = 3.3V IOUT = 0 mA CMOS Levels Notes: 5. VIL(min.) = –2.0V for pulse durations less than 20 ns. 6. TA is the “Instant-On” case temperature. Document #: 38-05014 Rev. *F Page 3 of 13 [+] Feedback CY62157CV30/33 Electrical Characteristics Over the Operating Range CY62157CV33-70 Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –1.0 mA VCC = 3.0V VOL Output LOW Voltage IOL = 2.1 mA VCC = 3.0V VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current f = fMAX = 1/tRC ICC f = 1 MHz ISB1 ISB2 Automatic CE Power-Down Current—CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE,WE,BHE,and BLE) Automatic CE Power-Down Current—CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V Min. Typ.[2] Max. 2.4 Unit V 0.4 V 2.2 VCC + 0.3V V –0.3 0.8 V Auto-A –1 +1 µA Auto-E –10 +10 µA Auto-A –1 +1 µA Auto-E –10 +10 µA 5.5 12 mA 7 15 1.5 3 VCC = 3.6V Auto-A IOUT = 0 mA Auto-E CMOS Levels Auto-A/ Auto-E Auto-A 10 30 µA Auto-E 10 80 µA Auto-A 10 30 µA Auto-E 10 80 µA Thermal Resistance[7] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board FBGA Unit 55 °C/W 16 °C/W Note: 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05014 Rev. *F Page 4 of 13 [+] Feedback CY62157CV30/33 Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ.) AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT R2 30 pF INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 90% 10% GND Rise TIme: 1 V/ns Fall Time: 1 V/ns THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V 3.3V Unit R1 1.105 1.216 ΚΩ R2 1.550 1.374 ΚΩ RTH 0.645 0.645 ΚΩ VTH 1.75 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[8] Chip Deselect to Data Retention Time tR[8] Operation Recovery Time Typ.[2] Max. Unit Auto-A 4 20 µA Auto-E 4 60 µA Conditions Min. 1.5 VCC = 1.5V, CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V V 0 ns tRC ns Data Retention Waveform[9] DATA RETENTION MODE VCC VCC(min.) tCDR VDR > 1.5 V VCC(min.) tR CE1 or BHE.BLE or CE2 Notes: 8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) >100 µs. 9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05014 Rev. *F Page 5 of 13 [+] Feedback CY62157CV30/33 Switching Characteristics Over the Operating Range [10] 70 ns Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns 25 ns 70 [11] tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[11, 12] tLZCE CE1 LOW and CE2 HIGH to Low-Z[11] tPU CE1 LOW and CE2 HIGH to Power-up tPD tDBE ns ns ns 10 High-Z[11, 12] CE1 HIGH or CE2 LOW to tHZBE 10 5 tHZCE tLZBE[11] ns ns 25 ns CE1 HIGH or CE2 LOW to Power-down 70 ns BHE/BLE LOW to Data Valid 70 ns BHE/BLE LOW to Low-Z[13] BHE/BLE HIGH to High-Z[11, 12] 0 ns 5 ns 25 ns Write Cycle[14] tWC Write Cycle Time 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 60 ns tAW Address Set-up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BHE/BLE Pulse Width 60 ns tSD Data Set-up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High-Z[11, 12] WE HIGH to Low-Z[11] 25 5 ns ns Notes: 10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. When both byte enables are toggled together this value is 10 ns. 14. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. Document #: 38-05014 Rev. *F Page 6 of 13 [+] Feedback CY62157CV30/33 Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[16, 17] ADDRESS tRC CE1 CE2 tACE OE tHZBE BHE/BLE tLZBE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 15. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 16. WE is HIGH for Read cycle. 17. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05014 Rev. *F Page 7 of 13 [+] Feedback CY62157CV30/33 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[14, 18, 19] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 20 tHZOE Notes: 18. Data I/O is high-impedance if OE = VIH. 19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 20. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05014 Rev. *F Page 8 of 13 [+] Feedback CY62157CV30/33 Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 20 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[19] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATAI/O NOTE 20 DATAIN VALID tHZWE Document #: 38-05014 Rev. *F tHD tLZWE Page 9 of 13 [+] Feedback CY62157CV30/33 Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O tHD DATAIN VALID NOTE 20 Truth Table CE1 CE2 WE OE H X X X X X High Z Deselect/Power-Down Standby (ISB) X L X X X X High Z Deselect/Power-Down Standby (ISB) X X X X H H High Z Deselect/Power-Down Standby (ISB) L H H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H H L L H Data Out (I/O8–I/O15); Read I/O0–I/O7 in High Z Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H L X L L Data In (I/OO–I/O15) Write Active (ICC) L H L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L H L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Document #: 38-05014 Rev. *F BHE BLE Inputs/Outputs Mode Power Page 10 of 13 [+] Feedback CY62157CV30/33 Typical DC and AC Characteristics [2] Operating Current vs. Supply Voltage 12.0 10.0 8.0 8.0 (f = fmax, 70ns) 6.0 4.0 2.0 12.0 10.0 (f = fmax, 70ns) 6.0 MoBL (f = 1 MHz) ICC (mA) MoBL ICC (mA) ICC (mA) 12.0 14.0 14.0 14.0 10.0 8.0 (f = fmax, 70ns) 6.0 4.0 4.0 2.0 2.0 (f = 1 MHz) 0.0 3.3 3.0 3.6 SUPPLY VOLTAGE (V) (f = 1 MHz) 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) 0.0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) MoBL 12.0 12.0 12.0 10.0 10.0 10.0 MoBL 8.0 ISB (µA) 8.0 MoBL ISB (µA) ISB (µA) Standby Current vs. Supply Voltage MoBL 8.0 6.0 6.0 6.0 4.0 4.0 4.0 2.0 2.0 2.0 0 0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) 0 3.0 2.7 SUPPLY VOLTAGE (V) 3.3 3.0 3.3 3.6 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 60 MoBL 60 MoBL 50 50 40 40 40 30 30 30 20 TAA (ns) 50 TAA (ns) TAA (ns) 60 20 10 10 2.2 2.5 2.7 SUPPLY VOLTAGE (V) Document #: 38-05014 Rev. *F 20 10 0 0 0 2.7 MoBL 3.0 3.3 SUPPLY VOLTAGE (V) 3.0 3.3 3.6 SUPPLY VOLTAGE (V) Page 11 of 13 [+] Feedback CY62157CV30/33 Ordering Information Speed (ns) Package Diagram Ordering Code 70 CY62157CV30LL-70BAE 51-85128 Operating Range Package Type 48-Ball (6 mm x 10 mm x 1.2 mm) FBGA Automotive-E CY62157CV33LL-70BAXA Automotive-A CY62157CV33LL-70BAE Automotive-E Package Diagram 48-Ball (6 mm x 10 mm x 1.2 mm) FBGA (51-85128) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 10.00±0.10 10.00±0.10 1 F G H H 1.875 A A B 0.75 6.00±0.10 0.53±0.05 B 0.15 C 0.21±0.05 0.25 C 3.75 6.00±0.10 0.15(4X) 1.20 MAX 0.36 SEATING PLANE C 51-85128-*D MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05014 Rev. *F Page 12 of 13 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62157CV30/33 Document History Page Document Title: CY62157CV30/33 512K x 16 Static RAM Document Number: 38-05014 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106184 05/10/01 *A 107241 07/24/01 HRT/MGN New data sheet – Advance Information MGN Made corrections to Advance Information Added 55 ns bin *B 109621 03/11/02 MGN Changed from Advance Information to Final *C 114218 05/01/02 *D 238448 See ECN AJU Added Automotive Product Information *E 269729 See ECN SYT Added Automotive Product information for CY62157CV30 – 70 ns Added IIX and IOZ values for Automotive range of CY62157CV33 – 70 ns *F 498575 See ECN NXR Removed Industrial Operating Range Removed 55 ns speed bin Removed CY62157CV25 part number from the Product Offering Added Automotive-A operating range Updated the Ordering Information Table Document #: 38-05014 Rev. *F GUG/MGN Improved Typical and Max ICC values Page 13 of 13 [+] Feedback