CY62157E MoBL®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512 K × 16) Static RAM
Features
■
when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE
are HIGH). The input or output pins (I/O0 through I/O15) are
placed in a high impedance state when:
Very high speed: 45 ns
❐ Industrial: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■
Wide voltage range: 4.5 V–5.5 V
■
Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A (Industrial)
■
Deselected (CE1HIGH or CE2 LOW)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Ultra low standby power
■
Easy memory expansion with CE1, CE2 and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of read and write modes.
Functional Description
The CY62157E is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
addresses are not toggling. Place the device into standby mode
The CY62157E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CE2
•
I/O8–I/O15
198 Champion Court
A17
A18
A15
A16
BHE
A14
BHE
I/O0–I/O7
COLUMN DECODER
CE1
BLE
Cypress Semiconductor Corporation
Document Number: 38-05695 Rev. *N
512K x 16
RAM Array
A11
A12
A13
Power Down
Circuit
SENSE AMPS
DATA IN DRIVERS
•
WE
CE2
OE
BLE
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised November 9, 2017
CY62157E MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 12
Document Number: 38-05695 Rev. *N
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY62157E MoBL®
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Range
Operating ICC, (mA)
f = 1 MHz
Min
Typ[1]
Max
Standby, ISB2 (A)
f = fmax
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
CY62157ELL
Industrial
4.5
5.0
5.5
45
1.8
3
18
25
2
8
CY62157ELL
Automotive
4.5
5.0
5.5
55
1.8
4
18
35
2
30
Pin Configurations
Figure 1. 44-pin TSOP II pinout [2, 3]
Figure 2. 48-ball VFBGA pinout [2]
Top View
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected on the die.
3. The 44-pin TSOP II package has only one chip enable (CE) pin.
Document Number: 38-05695 Rev. *N
Page 3 of 19
CY62157E MoBL®
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .............................. –65 °C to + 150 °C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch up Current .................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential .........................................................–0.5 V to 6.0 V
Device
Range
DC Voltage Applied to Outputs
in High Z State [4, 5] .........................................–0.5 V to 6.0 V
CY62157ELL
Industrial
Ambient
Temperature
VCC[6]
–40 °C to +85 °C 4.5 V to 5.5 V
Automotive –40 °C to +125 °C
DC Input Voltage [4, 5] .....................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Output HIGH
Voltage
VCC = 4.5 V
VOL
Output LOW
Voltage
IOL = 2.1 mA
VIH
Input HIGH
Voltage
VIL
VOH
VCC = 5.5 V
IOH = –1 mA
Min
Typ
2.4
–
–
–
–
–
VCC = 4.5 V to 5.5 V
2.2
Input LOW
Voltage
VCC = 4.5 V to 5.5 V
IIX
Input Leakage
Current
IOZ
ICC
[7]
55 ns (Automotive)
Max
Min
Typ [7]
Max
–
2.4
–
–
3.4
V
[8]
–
0.4
–
–
0.4
V
–
VCC + 0.5
2.2
–
VCC + 0.5
V
–0.5
–
0.8
–0.5
–
0.8
V
GND < VI < VCC
–1
–
+1
–4
–
+4
A
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
–
+1
–4
–
+4
A
VCC Operating
Supply Current
f = fmax = 1/tRC
–
18
25
–
18
35
mA
–
1.8
3
–
1.8
4
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
3.4
[8]
Unit
–
f = 1 MHz
IOH = –0.1 mA
45 ns (Industrial)
ISB1 [9]
Automatic CE
Power Down
Current – CMOS
Inputs
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = VCC(max)
–
2
8
–
2
30
A
ISB2 [9]
Automatic CE
Power Down
Current – CMOS
Inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
2
8
–
2
30
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5V, please refer to Application Note AN6081 for technical details and options you may consider.
9. Chip enables (CE1 and CE2) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 38-05695 Rev. *N
Page 4 of 19
CY62157E MoBL®
Capacitance
Parameter [10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [10]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II 48-ball VFBGA Unit
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
55.84
48.34
°C/W
15.79
8.78
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
OUTPUT
R1
3V
10%
GND
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
Values
Unit
R1
1800
R2
990
RTH
639
VTH
1.77
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05695 Rev. *N
Page 5 of 19
CY62157E MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR[12]
Data Retention Current
tCDR [13]
Chip Deselect to Data
Retention Time
tR [14]
Operation Recovery Time
Min
Typ [11]
Max
Unit
2
–
–
V
Industrial
–
–
8
A
Automotive
–
–
30
0
–
–
ns
CY62157ELL-45
45
–
–
ns
CY62157ELL-55
55
–
–
Conditions
VCC = 2 V, CE1 > VCC – 0.2 V or
CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 4. Data Retention Waveform [15]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2 V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Chip enables (CE1 and CE2) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05695 Rev. *N
Page 6 of 19
CY62157E MoBL®
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
45 ns (Industrial)
Description
55 ns (Automotive)
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
45
–
55
–
ns
tAA
Address to Data Valid
–
45
–
55
ns
tOHA
Data Hold from Address Change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
–
45
–
55
ns
tDOE
OE LOW to Data Valid
–
22
–
25
ns
tLZOE
OE LOW to Low Z[18]
5
–
5
–
ns
Z[18, 19]
–
18
–
20
ns
CE1 LOW and CE2 HIGH to Low
Z[18]
10
–
10
–
ns
tHZCE
CE1 HIGH and CE2 LOW to High
Z[18, 19]
–
18
–
20
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to Power Down
–
45
–
55
ns
tDBE
BLE/BHE LOW to Data Valid
–
45
–
55
ns
10
–
10
–
ns
–
18
–
20
ns
45
–
55
–
ns
ns
tHZOE
tLZCE
OE HIGH to High
Z[18]
tLZBE
BLE/BHE LOW to Low
tHZBE
BLE/BHE HIGH to High Z[18, 19]
Write Cycle
tWC
[20, 21]
Write Cycle Time
tSCE
CE1 LOW and CE2 HIGH to Write End
35
–
40
–
tAW
Address Setup to Write End
35
–
40
–
ns
tHA
Address Hold from Write End
0
–
0
–
ns
tSA
Address Setup to Write Start
0
–
0
–
ns
ns
tPWE
WE Pulse Width
35
–
40
–
tBW
BLE/BHE LOW to Write End
35
–
40
–
ns
tSD
Data Setup to Write End
25
–
25
–
ns
tHD
Data Hold from Write End
0
–
0
–
ns
Z[18, 19]
–
18
–
20
ns
10
–
10
–
ns
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z[18]
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
18. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. All signals must be active to initiate a write
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
21. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 38-05695 Rev. *N
Page 7 of 19
CY62157E MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [22, 23]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [23, 24]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
22. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
23. WE is HIGH for read cycle.
24. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 38-05695 Rev. *N
Page 8 of 19
CY62157E MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [25, 26, 27]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
WE
tPWE
tBW
BHE/BLE
tHD
OE
DATA I/O
tHA
tSA
tSD
NOTE 28
VALID DATA
tHZOE
Notes
25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
26. Data I/O is high impedance if OE = VIH.
27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *N
Page 9 of 19
CY62157E MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled) [29, 30, 31]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 32
tHD
VALID DATA
tHZOE
Notes
29. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
30. Data I/O is high impedance if OE = VIH.
31. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
32. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *N
Page 10 of 19
CY62157E MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [33, 34]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 35
tHD
VALID DATA
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [33]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 35
tHD
VALID DATA
Notes
33. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
34. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
35. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *N
Page 11 of 19
CY62157E MoBL®
Truth Table
CE1
H
CE2
WE
OE
BHE
BLE
[36]
X
X
X
X
X
X[36]
Inputs/Outputs
Mode
Power
High Z
Deselect/Power Down
Standby (ISB)
L
X
X
X
X
High Z
Deselect/Power Down
Standby (ISB)
[36]
X
X
H
H
High Z
Deselect/Power Down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
[36]
X
X
Note
36. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05695 Rev. *N
Page 12 of 19
CY62157E MoBL®
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
45
CY62157ELL-45ZSXI
51-85087 44-pin TSOP Type II (Pb-free)
Industrial
55
CY62157ELL-55ZSXE
51-85087 44-pin TSOP Type II (Pb-free)
Automotive-E
CY62157ELL-55BVXE
51-85150 48-ball VFBGA (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 5
7
E
LL - XX XX X X
Temperature Range: X = I or E
I = Industrial; E = Automotive-E
Pb-free
Package Type: XX = ZS or BV
ZS = 44-pin TSOP II
BV = 48-ball VFBGA
Speed Grade: XX = 45 ns or 55 ns
Low Power
Process Technology: E = 90 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: 621= MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05695 Rev. *N
Page 13 of 19
CY62157E MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 38-05695 Rev. *N
Page 14 of 19
CY62157E MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05695 Rev. *N
Page 15 of 19
CY62157E MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
µA
microampere
RAM
Random Access Memory
µs
microsecond
SRAM
Static Random Access Memory
mA
milliampere
mm
millimeter
TTL
Transistor-Transistor Logic
TSOP
Thin Small Outline Package
VFBGA
Very Fine-Pitch Ball Grid Array
WE
Write Enable
Document Number: 38-05695 Rev. *N
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 16 of 19
CY62157E MoBL®
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512 K × 16) Static RAM
Document Number: 38-05695
Rev.
ECN No.
Issue Date
Orig. of
Change
**
291273
See ECN
PCI
New data sheet.
*A
457689
See ECN
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
467033
See ECN
NXR
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz
Changed the ISB2(typ) value of Automotive from 5 A to 1.8 A
Modified footnote #4 to include current limit
Updated the Ordering Information table
*C
569114
See ECN
VKN
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
*D
925501
See ECN
VKN
Added footnote #9 related to ISB2 and ICCDR
Added footnote #14 related AC timing parameters
*E
1045801
See ECN
VKN
Converted Automotive specs from preliminary to final
*F
2934396
06/03/10
VKN
Added footnote #23 related to chip enable
Updated Package Diagrams.
Updated to new template.
*G
3110053
12/14/2010
PRAS
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*H
3269641
05/30/2011
RAME
Removed the note “For best practice recommendations, please refer to the
Cypress application note AN1064, SRAM System Guidelines.” and its
reference in Functional Description.
Updated Electrical Characteristics.
Updated Data Retention Characteristics.
Added Acronyms and Units of Measure.
Updated to new template.
*I
4013958
06/05/2013
MEMJ
Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH parameter
and added maximum value corresponding to that Test Condition.
Added Note 8 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “VCC = 5.5 V, IOH = –0.1 mA”.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
*J
4102449
08/22/2013
VINI
Document Number: 38-05695 Rev. *N
Description of Change
Updated Switching Characteristics:
Updated Note 17.
Updated to new template.
Page 17 of 19
CY62157E MoBL®
Document History Page (continued)
Document Title: CY62157E MoBL®, 8-Mbit (512 K × 16) Static RAM
Document Number: 38-05695
Rev.
ECN No.
Issue Date
Orig. of
Change
*K
4410589
06/17/2014
VINI
Updated Switching Characteristics:
Added Note 21 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 34 and referred the same note in Figure 9.
Completing Sunset Review.
*L
4576475
11/21/2014
VINI
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*M
4795615
06/12/2015
VINI
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of θJA corresponding to 44-pin TSOP II package from 77 °C/W
to 55.84 °C/W.
Changed value of θJA corresponding to 48-ball VFBGA package from 72 °C/W
to 48.34 °C/W.
Changed value of θJC corresponding to 44-pin TSOP II package from 13 °C/W
to 15.79 °C/W.
Changed value of θJC corresponding to 48-ball VFBGA package from
8.86 °C/W to 8.78 °C/W.
Updated AC Test Loads and Waveforms:
Updated Figure 3:
Replaced “V” with “VTH” in bottom part.
Updated to new template.
Completing Sunset Review.
*N
5962457
11/09/2017
Document Number: 38-05695 Rev. *N
Description of Change
AESATMP8 Updated logo and Copyright.
Page 18 of 19
CY62157E MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05695 Rev. *N
Revised November 9, 2017
Page 19 of 19
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