CY62157EV30 MoBL®
8-Mbit (512K × 16) Static RAM
8-Mbit (512K × 16) Static RAM
Features
Functional Description
■
Thin small outline package (TSOP) I package configurable as
512K × 16 or 1M × 8 static RAM (SRAM)
■
High speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62157DV30
■
Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A (Industrial)
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
■
Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free and non Pb-free 48-ball very fine-pitch ball
grid array (VFBGA), Pb-free 44-pin thin small outline package
(TSOP) II and 48-pin TSOP I packages
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input or output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE1HIGH or CE2 LOW), the outputs are
disabled (OE HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is active (CE1
LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 13
for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
512 K × 16/1 M x 8
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
BHE
WE
CE2
CE1
BHE
A11
A12
A13
A14
A15
A16
A17
A18
Power Down
Circuit
OE
BLE
CE2
CE1
BLE
Cypress Semiconductor Corporation
Document Number: 38-05445 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 10, 2017
CY62157EV30 MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................13
Document Number: 38-05445 Rev. *Q
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagrams ..........................................................15
Acronyms ........................................................................18
Document Conventions .................................................18
Units of Measure .......................................................18
Document History Page .................................................19
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC® Solutions .......................................................21
Cypress Developer Community .................................21
Technical Support ......................................................21
Page 2 of 21
CY62157EV30 MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE 2
I/O8
BHE
A3
A4
CE 1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
A17
A7
I/O3
VCC
D
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
VSS I/O11
VCC
I/O12
Figure 2. 44-pin TSOP II pinout (Top View) [2]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
A
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
Figure 3. 48-pin TSOP I pinout (Top View) [1, 3]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Product
CY62157EV30LL
Range
VCC Range (V)
Min
Typ [4]
Max
Industrial/Automotive-A
2.2
3.0
3.6
Automotive-E
2.2
3.0
3.6
Speed
(ns)
Power Dissipation
Operating ICC, (mA)
f = 1 MHz
f = fmax
Standby, ISB2
(A)
Typ [4]
Max
Typ [4]
Max
Typ [4]
45
1.8
3
18
25
2
8
55
1.8
4
18
35
2
30
Max
Notes
1. NC pins are not connected on the die.
2. The 44-pin TSOP II package has only one chip enable (CE) pin.
3. The BYTE pin in the 48-pin TSOP I package must be tied HIGH to use the device as a 512 K × 16 SRAM. The 48-pin TSOP I package can also be used as a 1 M × 8
SRAM by tying the BYTE signal LOW. In the 1 M x 8 configuration, Pin 45 is A19, while BHE, BLE and I/O8 to I/O14 pins are not used.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05445 Rev. *Q
Page 3 of 21
CY62157EV30 MoBL®
Maximum Ratings
Output Current into Outputs (LOW) ............................20 mA
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature .............................. –65 °C to + 150 °C
Ambient Temperature
with Power Applied ................................. –55 °C to + 125 °C
Supply Voltage
to Ground Potential ............–0.3 V to 3.9 V (VCCmax + 0.3 V)
DC Voltage Applied to Outputs
in High Z State [5, 6] ...........–0.3 V to 3.9 V (VCCmax + 0.3 V)
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Latch-Up Current ...................................................> 200 mA
Operating Range
Device
Ambient
Temperature
Range
CY62157EV30LL
VCC [7]
Industrial / –40 °C to +85 °C
Automotive-A
2.2 V to
3.6 V
Automotive-E –40 °C to +125 °C
DC Input Voltage [5, 6] .......–0.3 V to 3.9 V (VCC max + 0.3 V)
Electrical Characteristics
Over the Operating Range
Parameter
Description
Output HIGH voltage
VOH
Output LOW voltage
VOL
Input HIGH voltage
VIH
Input LOW voltage
VIL
Test Conditions
45 ns (Industrial/
Automotive-A)
55 ns (Automotive-E)
Unit
Min
Typ [8]
Max
Min
Typ [8]
Max
IOH = –0.1 mA
2.0
–
–
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
–
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
–
–
0.4
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
1.8
–
VCC + 0.3
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
–0.3
–
0.6
V
VCC = 2.7 V to 3.6 V
–0.3
–
0.8
–0.3
–
0.8
V
IIX
Input leakage current
–1
–
+1
–4
–
+4
A
IOZ
Output leakage current GND < VO < VCC, Output Disabled
–1
–
+1
–4
–
+4
A
ICC
VCC operating supply
current
–
18
25
–
18
35
–
1.8
3
–
1.8
4
mA
–
2
8
–
2
30
A
–
2
8
–
2
30
A
ISB1 [9]
GND < VI < VCC
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
Automatic CE power CE1 > VCC 0.2 V or CE2 < 0.2 V
down current – CMOS
inputs
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
ISB2
[9]
Automatic CE power CE1 > VCC – 0.2 V or CE2 < 0.2 V
down current – CMOS
inputs
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other
inputs can be left floating.
Document Number: 38-05445 Rev. *Q
Page 4 of 21
CY62157EV30 MoBL®
Capacitance
Parameter [10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball BGA
48-pin TSOP I 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
48.34
55.47
55.84
C/W
8.78
4.08
15.79
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
VCC
10%
GND
R2 Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05445 Rev. *Q
Page 5 of 21
CY62157EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Min
Typ [11]
Max
Unit
1.5
–
–
V
Industrial /
Automotive-A
–
2
5
A
Automotive-E
–
–
30
0
–
CY62157EV30LL-45
45
–
–
CY62157EV30LL-55
55
–
–
Conditions
VCC for data retention
VDR
ICCDR
[12]
Data retention current
VCC = 1.5 V,
CE1 > VCC – 0.2 V, CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR
[13]
Chip deselect to data
retention time
tR [14]
Operation recovery time
ns
ns
Data Retention Waveform
Figure 5. Data Retention Waveform [15]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec.
Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05445 Rev. *Q
Page 6 of 21
CY62157EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
45 ns (Industrial/
Automotive-A)
Description
Min
55 ns (Automotive-E)
Max
Min
Unit
Max
Read Cycle
tRC
Read cycle time
45
–
55
–
ns
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
5
–
5
–
ns
–
18
–
20
ns
CE1 LOW and CE2 HIGH to Low
Z[18]
10
–
10
–
ns
CE1 HIGH and CE2 LOW to High
Z[18, 19]
–
18
–
20
ns
ns
Z[18]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[18, 19]
tLZCE
tHZCE
tPU
CE1 LOW and CE2 HIGH to power up
0
–
0
–
tPD
CE1 HIGH and CE2 LOW to power down
–
45
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
45
–
55
ns
5
Z[18, 20]
–
10
–
ns
–
18
–
20
ns
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
ns
tLZBE
tHZBE
BLE/BHE LOW to Low
BLE/BHE HIGH to High
Z[18, 19]
Write Cycle [21, 22]
tWC
tBW
BLE/BHE LOW to write end
35
–
40
–
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
WE LOW to High
Z[18, 19]
–
18
–
20
ns
WE HIGH to Low
Z[18]
10
–
10
–
ns
tHZWE
tLZWE
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 4 on page 5.
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
18. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
20. If both byte enables are toggled together, this value is 10 ns.
21. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
22. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05445 Rev. *Q
Page 7 of 21
CY62157EV30 MoBL®
Switching Waveforms
Figure 6. Read Cycle No. 1 (Address Transition Controlled) [23, 24]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 7. Read Cycle No. 2 (OE Controlled) [24, 25]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
23. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.
24. WE is HIGH for read cycle.
25. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 38-05445 Rev. *Q
Page 8 of 21
CY62157EV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled) [26, 27, 28]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 29
VALID DATA
tHZOE
Notes
26. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
27. Data I/O is high impedance if OE = VIH.
28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *Q
Page 9 of 21
CY62157EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [30, 31, 32]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 33
tHD
VALID DATA
tHZOE
Notes
30. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
31. Data I/O is high impedance if OE = VIH.
32. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
33. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *Q
Page 10 of 21
CY62157EV30 MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [34, 35]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 36
tHD
VALID DATA
tHZWE
tLZWE
Notes
34. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
35. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
36. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *Q
Page 11 of 21
CY62157EV30 MoBL®
Switching Waveforms (continued)
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [37]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 38
tHD
VALID DATA
Notes
37. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
38. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *Q
Page 12 of 21
CY62157EV30 MoBL®
Truth Table
CE1
WE
OE
BHE
BLE
X
[39]
Mode
Power
X
X
X
X
X
[39]
High Z
Deselect/power down
Standby (ISB)
L
X
X
X
X
[39]
X
[39]
X
High Z
Deselect/power down
Standby (ISB)
X
X
H
H
High Z
Deselect/power down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0 –I/O7 );
High Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
H
CE2
Inputs/Outputs
Note
39. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05445 Rev. *Q
Page 13 of 21
CY62157EV30 MoBL®
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
CY62157EV30LL-45BVI
51-85150 48-ball VFBGA
CY62157EV30LL-45BVIT
51-85150 48-ball VFBGA
CY62157EV30LL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
CY62157EV30LL-45BVXIT
51-85150 48-ball VFBGA (Pb-free)
CY62157EV30LL-45ZSXI
51-85087 44-pin TSOP Type II (Pb-free)
CY62157EV30LL-45ZSXIT
51-85087 44-pin TSOP Type II (Pb-free)
CY62157EV30LL-45ZXI
51-85183 48-pin TSOP Type I (Pb-free)
CY62157EV30LL-45ZXIT
51-85183 48-pin TSOP Type I (Pb-free)
CY62157EV30LL-45BVXA
51-85150 48-ball VFBGA (Pb-free)
CY62157EV30LL-45BVXAT
51-85150 48-ball VFBGA (Pb-free)
CY62157EV30LL-45ZSXA
51-85087 44-pin TSOP Type II (Pb-free)
CY62157EV30LL-45ZSXAT
51-85087 44-pin TSOP Type II (Pb-free)
CY62157EV30LL-45ZXA
51-85183 48-pin TSOP Type I (Pb-free)
CY62157EV30LL-45ZXAT
51-85183 48-pin TSOP Type I (Pb-free)
CY62157EV30LL-55ZSXE
51-85087 44-pin TSOP Type II (Pb-free)
CY62157EV30LL-55ZSXET
51-85087 44-pin TSOP Type II (Pb-free)
CY62157EV30LL-55ZXE
51-85183 48-pin TSOP Type I (Pb-free)
CY62157EV30LL-55ZXET
51-85183 48-pin TSOP Type I (Pb-free)
Operating
Range
Industrial
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 5
7
E V30 LL -
XX XX
X
X
X
Option: T- Tape & Reel; Blank - Std
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = BV or ZS or Z
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Z = 48-pin TSOP I
Speed Grade: XX = 45 ns or 55 ns
Low Power
Voltage
Process Technology: E = 90 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05445 Rev. *Q
Page 14 of 21
CY62157EV30 MoBL®
Package Diagrams
Figure 12. 48-pin VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *H
Document Number: 38-05445 Rev. *Q
Page 15 of 21
CY62157EV30 MoBL®
Package Diagrams (continued)
Figure 13. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05445 Rev. *Q
Page 16 of 21
CY62157EV30 MoBL®
Package Diagrams (continued)
Figure 14. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
NOTES:
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3.
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
b1
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
N
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
CYPRESS
Company Confidential
Document Number: 38-05445 Rev. *Q
Page 17 of 21
CY62157EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
μA
microampere
RAM
Random Access Memory
μs
microsecond
SRAM
Static Random Access Memory
mA
milliampere
TSOP
Thin Small Outline Package
mm
millimeter
VFBGA
Very Fine-Pitch Ball Grid Array
ns
nanosecond
WE
Write Enable
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-05445 Rev. *Q
Symbol
Unit of Measure
Page 18 of 21
CY62157EV30 MoBL®
Document History Page
Document Title: CY62157EV30 MoBL®, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05445
Revision
ECN
Orig. of
Change
Submission
Date
**
202940
AJU
See ECN
New data sheet.
*A
291272
SYT
See ECN
Changed status from Advance Information to Preliminary.
Removed 48-TSOP I Package and the associated footnote
Added footnote stating 44 TSOP II Package has only one CE on Page # 2
Changed VCC stabilization time in footnote #7 from 100 s to 200 s
Changed ICCDR from 4 to 4.5 A
Changed tOHA from 6 to 10 ns for both 35 and 45 ns Speed Bins
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for 35 and
45 ns Speed Bins respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed Bins
respectively
Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns Speed
Bins respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively
Added Lead-Free Package Information
*B
444306
NXR
See ECN
Changed status from Preliminary to Final.
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU.
Removed 35 ns speed bin
Removed “L” bin
Added 48 pin TSOP I package
Added Automotive product information.
Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28
mA to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 Max value from 4.5 A to 8 A and Typ value from
0.9 A to 2 A respectively.
Modified ISB1 test condition to include BHE, BLE
Updated Thermal Resistance table.
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR Max value from 4.5 A to 5 A
Corrected tR in Data Retention Characteristics from 100 s to tRC ns.
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tLZBE from 6 to 5
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Added footnote #15
Updated the ordering Information and replaced the Package Name column
with Package Diagram.
*C
467052
NXR
See ECN
Modified Data sheet to include x8 configurability.
Updated the Ordering Information table
*D
925501
VKN
See ECN
Removed Automotive-E information
Added Preliminary Automotive-A information
Added footnote #10 related to ISB2 and ICCDR
Added footnote #15 related AC timing parameters
Document Number: 38-05445 Rev. *Q
Description of Change
Page 19 of 21
CY62157EV30 MoBL®
Document History Page (continued)
Document Title: CY62157EV30 MoBL®, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05445
Revision
ECN
Orig. of
Change
Submission
Date
*E
1045801
VKN
See ECN
Converted Automotive-A specs from preliminary to final
Updated footnote #9
*F
2724889
NXR /
AESA
06/26/09
Added Automotive-E information
Included -45ZXA/-55ZSXE/-55ZXE parts in the Ordering Information table
*G
2927528
VKN
05/04/2010
Renamed “DNU” pins as “NC” for 48 TSOP I package
Added footnote #24 related to chip enable
Added Contents
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
*H
3110053
PRAS
12/14/2010
Changed Table Footnotes to Notes.
Added Ordering Code Definitions under Ordering Information.
*I
3269771
RAME
05/30/2011
Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”).
Updated Electrical Characteristics.
Updated Data Retention Characteristics.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*J
3578601
TAVA
04/11/2012
Updated Package Diagrams.
*K
4102449
VINI
08/22/2013
Updated Switching Characteristics:
Updated Note 17.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
*L
4126231
VINI
09/18/2013
Updated Switching Characteristics:
Updated Note 17 (Removed last sentence from Note 17 and added the same
sentence as a new note namely Note 18).
*M
4214977
MEMJ
12/09/2013
Updated Pin Configurations:
Updated Note 3 (Removed ‘NC’ mentioned at the end of the note).
*N
4578508
MEMJ
11/24/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 22 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 35 and referred the same note in Figure 10.
*O
4748627
NILE
04/30/2015
Updated Package Diagrams:
spec 51-85183 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*P
5320972
NILE
06/23/2016
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated values of JA, JC parameters corresponding to all packages.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*Q
5731504
NILE
05/10/2017
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05445 Rev. *Q
Description of Change
Page 20 of 21
CY62157EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05445 Rev. *Q
Revised May 10, 2017
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation.
Page 21 of 21
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