CY62157E_09

CY62157E MoBL® 8-Mbit (512K x 16) Static RAM Features • Very high speed: 45 ns • Wide voltage range: 4.5V–5.5V • Ultra-low standby power —Typical Standby current: 2 µA —Maximum Standby current: 8 µA (Industrial) • Ultra-low active power — Typical active current: 1.8 mA @ f = 1 MHz • Ultra-low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free 44-pin TSOP II and 48-ball VFBGA package also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (IO0 through IO15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See the truth table at the back of this data sheet for a complete description of read and write modes. Functional Description[1] The CY62157E is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 512K x 16 RAM Array SENSE AMPS IO0–IO7 IO8–IO15 COLUMN DECODER BHE WE A11 A12 A13 A15 A14 A17 A18 A16 CE2 CE1 OE BLE POWER-DOWN CIRCUIT BHE BLE CE2 CE1 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05695 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 21, 2006 [+] Feedback CY62157E MoBL® Pin Configuration[2, 3] TSOP II Top View A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 A8 A9 A10 A11 A12 A13 1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO 10 IO11 IO 12 IO 13 NC A8 VFBGA Top View 4 3 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO 1 IO3 IO 4 IO 5 WE A11 6 CE2 IO 0 IO 2 Vcc Vss IO 6 IO 7 NC A B C D E F G H Product Portfolio Power Dissipation VCC Range (V) Product CY62157E-45 CY62157E-55[5] Range Ind’l Auto Min 4.5 4.5 Typ[4] 5.0 5.0 Max 5.5 5.5 45 55 Speed (ns) Operating ICC, (mA) f = 1MHz Typ[4] 1.8 1.8 Max 3 4 f = fmax Typ[4] 18 18 Max 25 35 Standby, ISB2 (µA) Typ[4] 2 2 Max 8 30 Notes: 2. NC pins are not connected on the die. 3. The 44-pin TSOP II package has only one chip enable (CE) pin. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 5. Automotive product information is Preliminary. Document #: 38-05695 Rev. *C Page 2 of 12 [+] Feedback CY62157E MoBL® Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Supply Voltage to Ground Potential .......................................................... –0.5V to 6.0V DC Voltage Applied to Outputs in High Z State[6, 7] ........................................... –0.5V to 6.0V DC Input Voltage[6, 7] ........................................–0.5V to 6.0V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA Operating Range Device CY62157E Range Industrial Ambient Temperature –40°C to +85°C VCC[8] 4.5V to 5.5V Automotive –40°C to +125°C Electrical Characteristics (Over the Operating Range) 45 ns (Industrial) Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Test Conditions IOH = –1 mA IOL = 2.1 mA VCC = 4.5V VCC = 4.5V 2.2 –0.5 –1 –1 18 1.8 2 Min 2.4 0.4 VCC + 0.5 0.8 +1 +1 25 3 8 2.2 –0.5 –1 –1 18 1.8 2 Typ [4] 55 ns (Automotive) Min 2.4 0.4 VCC + 0.5 0.8 +1 +1 35 4 30 mA µA Typ[4] Max Unit V V V V µA µA Max VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V GND < VI < VCC Output Leakage GND < VO < VCC, Output Disabled Current VCC Operating Supply Current Automatic CE Power-Down Current — CMOS Inputs Automatic CE Power-Down Current — CMOS Inputs f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA f = 1 MHz CMOS levels CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V, VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60V CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V ISB1 ISB2 2 8 2 30 µA Capacitance[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes: 6. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA. 7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 8. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05695 Rev. *C Page 3 of 12 [+] Feedback CY62157E MoBL® Thermal Resistance[9] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board TSOP II VFBGA 77 13 72 8.86 Unit °C/W °C/W AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V R2 3V 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Parameters R1 R2 RTH VTH Values 1800 990 639 1.77 Unit Ω Ω Ω V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [9] Description VCC for Data Retention Data Retention Current Conditions Min 2 Typ[4] Max Unit V µA Industrial VCC=2V, CE1> VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Automotive 0 tRC 8 30 Chip Deselect to Data Retention Time Operation Recovery Time ns ns tR[10] Data Retention Waveform[11] DATA RETENTION MODE VCC CE1or BHE.BLE CE2 VCC(min) tCDR VDR > 2 V VCC(min) tR Notes: 10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05695 Rev. *C Page 4 of 12 [+] Feedback CY62157E MoBL® Switching Characteristics Over the Operating Range [12] 45 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[15] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[13, 14] 10 WE HIGH to Low-Z[13] 45 35 35 0 0 35 35 25 0 18 10 55 40 40 0 0 40 40 25 0 20 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[13] OE HIGH to High Z [13, 14] [13] 55 ns Max Min 55 45 55 10 45 22 55 25 5 18 20 10 18 20 0 45 45 55 55 10 18 20 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min 45 10 5 10 0 CE1 LOW and CE2 HIGH to Low Z CE1 HIGH and CE2 LOW to High Z[13, 14] CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH and CE2 LOW to Power-Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[13] BLE/BHE HIGH to HIGH Z[13, 14] 10 Notes: 12. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. Document #: 38-05695 Rev. *C Page 5 of 12 [+] Feedback CY62157E MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[16, 17] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle 2 (OE Controlled)[17, 18] ADDRESS CE1 tRC tPD CE2 BHE/BLE tLZBE tDBE tHZBE tHZCE tACE OE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU tDOE DATA VALID tHZOE HIGH IMPEDANCE ICC ISB 50% 50% Notes: 16. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05695 Rev. *C Page 6 of 12 [+] Feedback CY62157E MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[15, 19, 20, 21] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tBW tPWE tHA BHE/BLE OE tSD DATA IO See Note 21 tHD VALID DATA tHZOE Write Cycle 2 (CE1 or CE2 Controlled)[15, 19, 20, 21] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tBW tHA BHE/BLE OE tSD DATA IO See Note 21 tHD VALID DATA tHZOE Notes: 19. Data IO is high impedance if OE = VIH. 20. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 21. During this period, the IOs are in output state and input signals should not be applied. Document #: 38-05695 Rev. *C Page 7 of 12 [+] Feedback CY62157E MoBL® Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[20, 21] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tHA tPWE WE tSA tSD DATA IO See Note 21 tHD VALID DATA tHZWE tLZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[20, 21] tWC ADDRESS CE1 CE2 tAW tBW BHE/BLE tSA WE tPWE tSD DATA IO See Note 21 tSCE tHA tHD VALID DATA Document #: 38-05695 Rev. *C Page 8 of 12 [+] Feedback CY62157E MoBL® Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (IO0–IO15) Data Out (IO0–IO7); High Z (IO8–IO15) High Z (IO0–IO7); Data Out (IO8–IO15) High Z High Z High Z Data In (IO0–IO15) Data In (IO0–IO7); High Z (IO8–IO15) High Z (IO0–IO7); Data In (IO8–IO15) Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 45 55 Ordering Code CY62157ELL-45ZSXI CY62157ELL-55ZSXE CY62157ELL-55BVXE Package Diagram 51-85087 51-85087 51-85150 Package Type 44-pin Thin Small Outline Package Type II (Pb-free) 44-pin Thin Small Outline Package Type II (Pb-free) 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Operating Range Industrial Automotive Document #: 38-05695 Rev. *C Page 9 of 12 [+] Feedback CY62157E MoBL® Package Diagrams 44-pin TSOP II (51-85087) 51-85087-*A Document #: 38-05695 Rev. *C Page 10 of 12 [+] Feedback CY62157E MoBL® Package Diagrams (continued) 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.00±0.10 8.00±0.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.00±0.10 A 1.875 0.75 3.75 B 6.00±0.10 0.55 MAX. 0.25 C 0.15(4X) 0.21±0.05 0.10 C 51-85150-*D SEATING PLANE 0.26 MAX. C 1.00 MAX MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05695 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62157E MoBL® Document History Page Document Title: CY62157E MoBL®, 8-Mbit (512K x 16) Static RAM Document Number: 38-05695 REV. ** *A ECN NO. Issue Date 291273 457689 See ECN See ECN Orig. of Change PCI NXR Description of Change New data sheet Added Automotive Product Removed Industrial Product Removed 35 ns and 45 ns speed bins Removed “L” bin Updated AC Test Loads table Corrected tR in Data Retention Characteristics from 100 µs to tRC ns Updated the Ordering Information and replaced the Package Name column with Package Diagram Added Industrial Product (Final Information) Removed 48 ball VFBGA package and its relevant information Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz Changed the ISB2(typ) value of Automotive from 5 µA to 1.8 µA Modified footnote #4 to include current limit Updated the Ordering Information table Added 48 ball VFBGA package Updated Logic Block Diagram Added footnote #3 Updated the Ordering Information table *B 467033 See ECN NXR *C 569114 See ECN VKN Document #: 38-05695 Rev. *C Page 12 of 12 [+] Feedback