CY62158DV30L-55BVI

THIS SPEC IS OBSOLETE Spec No: 38-05391 Spec Title: CY62158DV30 MoBL, 8-Mbit (1024K x 8) MoBL Static RAM Sunset Owner: Anuj Chakrapani (AJU) Replaced by: None CY62158DV30 MoBL® 8-Mbit (1024K x 8) MoBL® Static RAM This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption by 85% when deselected (CE1 HIGH or CE2 LOW). Features • Very high speed: 45 ns, 55 ns and 70 ns — Wide voltage range: 2.20V – 3.60V • Ultra-low active power — Typical active current:1.5 mA @ f = 1 MHz — Typical active current: 12 mA @ f = fmax • Ultra-low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered in a 48-ball BGA, 48-pin TSOPI, and 44-pin TSOPII Functional Description[1] The CY62158DV30 is a high-performance CMOS static RAMs organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. Writing to the device is accomplished by taking Chip Enable 1 (CE1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). See the truth table for a complete description of read and write modes. Logic Block Diagram I/O1 1024K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 Data in Drivers I/O3 I/O4 I/O5 COLUMN DECODER CE1 CE2 I/O6 POWER DOWN I/O7 A13 A14 A15 A16 A17 A18 A19 WE OE Note: 1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05391 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 23, 2010 [+] Feedback CY62158DV30 MoBL® Pin Configuration[2, 3, 4] FBGA Top View 1 2 3 4 5 6 DNU OE A0 A1 A2 CE2 A DNU DNU A3 A4 CE1 DNU B I/O0 DNU A5 A6 DNU I/O4 C VSS I/O1 A17 A7 I/O5 VCC D VCC I/O2 DNU A16 I/O6 VSS E I/O3 DNU A14 A15 DNU I/O7 F DNU NC A12 A13 WE DNU G A18 A8 A9 A10 A11 A19 H A A 48TSOPI 44 TSOPII Top View Top View A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU DNU DNU A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss A19 I/O7 DNU I/O6 DNU I/O5 DNU I/O4 Vcc DNU I/O3 DNU I/O2 DNU I/O1 DNU I/O0 OE Vss CE1 A0 A4 A3 A2 A1 A0 CE1 DNU DNU I/O0 I/O1 VCC VSS I/O2 I/O3 DNU DNU WE A19 A18 A17 A16 A15 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CE2 A8 DNU DNU I/O7 I/O6 VSS VCC I/O5 I/O4 DNU DNU A9 A10 A11 A12 A13 A14 Notes: 2. NC pins are not internally connected to the die. 3. DNU pins have to be left floating. 4. The BYTE pin in the TSOPI package has to be tied LOW to use the device as 1M x 8 SRAM. The 48-TSOPI package can also be used as a 512K × 16 SRAM by tying the BYTE signal HIGH. For 512K x 16 functionality, please refer to the CY62157DV30 data sheet. Document #: 38-05391 Rev. *E Page 2 of 11 [+] Feedback CY62158DV30 MoBL® Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................... 55°C to +125°C Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Supply Voltage to Ground Potential .–0.3V to Vcc(max) + 0.3V Product Ambient Temperature (TA) Range DC Voltage Applied to Outputs in High-Z State[5, 6] ......................... –0.3V to VCC(max) + 0.3V CY62158DV30L DC Input Voltage[5, 6] ..................... –0.3V to VCC(max) + 0.3V CY62158DV30LL VCC[7] Industrial –40°C to +85°C 2.2V – 3.6V Product Portfolio Power Dissipation Operating ICC (mA) VCC Range (V) Max. Speed (ns) Typ.[8] 3.0 3.6 45,55,70 3.0 3.6 45,55,70 Min. Typ.[8] CY62158DV30L 2.2 CY62158DV30LL 2.2 Product f = 1 MHz f = fmax Standby ISB2(μA) Max. Typ.[8] Max. Typ.[8] Max. 1.5 3 12 20 2 20 1.5 3 12 15 2 8 Electrical Characteristics Over the Operating Range CY62158DV30 Parameter Description Min. Typ.[8] Test Conditions VOH Output HIGH Voltage IOH = –0.1 mA VCC = 2.20V 2.0 IOH = –1.0 mA VCC = 2.70V 2.4 VOL Output LOW Voltage IOL = 0.1 mA VCC = 2.20V IOL = 2.1mA VCC = 2.70V VIH Input HIGH Voltage VCC = 2.2V to 2.7V VIIL Input LOW Voltage VCC= 2.7V to 3.6V IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC Max. V V V 0.4 V VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V V VCC = 2.2V to 2.7V –0.3 0.6 V –0.3 0.8 V –1 +1 μA –1 VCC = VCCmax L IOUT = 0 mA LL CMOS levels L 12 +1 μA 20 mA 15 mA 1.5 3 mA LL ISB2 0.4 1.8 f = 1 MHz ISB1 Unit 3 mA Automatic CE Power-down Current — CMOS Inputs CE1 > VCC− 0.2V, CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = 3.60V L 2 20 μA LL 2 8 Automatic CE Power-down Current — CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V L 2 20 LL 2 8 μA Notes: 5. VIL(min.) = –2.0V for pulse durations less than 20 ns. 6. VIH(max)= VCC+0.75V for pulse duration less than 20ns. 7. Full device AC operation assumes a 100 μs ramp time from 0 to Vcc(min) and 200 μs wait time after Vcc stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05391 Rev. *E Page 3 of 11 [+] Feedback CY62158DV30 MoBL® Capacitance[9, 10.] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Max. Unit 10 pF 10 pF Thermal Resistance Parameter Description ΘJA Thermal Resistance[9] (Junction to Ambient) ΘJC Thermal Resistance[9] (Junction to Case) Test Conditions BGA TSOP II TSOP I Unit Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 72 75.13 74.88 °C/W 8.86 8.95 8.6 °C/W AC Test Loads and Waveforms [11] R1 VCC ALL INPUT PULSES OUTPUT VCC R2 30 pF / 50 pF GND 10% 90% 10% 90% Fall time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.50V 3.0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[9] Chip Deselect to Data Retention Time tR[12] Operation Recovery Time Conditions Min. Typ.[8] Max. Unit 10 μA 4 μA 1.5 VCC = 1.5V L CE1 > VCC − 0.2V or CE2 VCC − 0.2V or VIN < 0.2V V 0 ns tRC ns Notes: 9. Tested initially and after any design or process changes that may affect these parameters. 10. The input capacitance on the CE2 pin is 15 pF. 11. Test condition for the 45 ns part is a load capacitance of 30 pF. 12. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 μs or stable at VCC(min.) > 100 μs. Document #: 38-05391 Rev. *E Page 4 of 11 [+] Feedback CY62158DV30 MoBL® Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5 V VCC(min) tR tCDR CE1 or CE2 Switching Characteristics Over the Operating Range [13] 45 ns [11] Parameter Description Min. Max. 55 ns Min. 70 ns Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 45 55 70 ns tDOE OE LOW to Data Valid 25 25 35 ns 45 10 [14] tLZOE OE LOW to Low Z tHZOE OE HIGH to High tHZCE CE1 HIGH or CE2 LOW to High Z tPU CE1 LOW and CE2 HIGH to Power-Up Write Cycle CE1 HIGH or CE2 LOW to Power-Down 10 0 45 ns 25 20 ns ns 25 10 55 ns ns 5 10 0 70 20 20 ns 10 5 10 [14, 15] tPD 55 15 CE1 LOW and CE2 HIGH to Low Z 70 10 5 Z[14, 15] [14] tLZCE 55 ns ns 25 ns [16] tWC Write Cycle Time 45 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 40 40 60 ns tAW Address Set-Up to Write End 40 40 60 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 35 40 45 ns tSD Data Set-Up to Write End 25 25 30 ns tHD Data Hold from Write End 0 0 0 ns tHZWE tLZWE WE LOW to High Z[14, 15] [14] WE HIGH to Low Z 15 10 20 10 25 10 ns ns Notes: 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05391 Rev. *E Page 5 of 11 [+] Feedback CY62158DV30 MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [17, 18] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE tPD tPU 50% 50% SUPPLY CURRENT Write Cycle No. 1(WE Controlled) HIGH IMPEDANCE ICC ISB [16, 20, 22] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE OE tSD DATA I/O tHD VALID DATA NOTE [20] tHZOE Notes: 17. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 18. WE is HIGH for read cycle. 19. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05391 Rev. *E Page 6 of 11 [+] Feedback CY62158DV30 MoBL® Switching Waveforms (continued) Write Cycle No. 2(CE1 or CE2 Controlled) [16, 20, 22] tWC ADDRESS tSCE CE1 tSA CE2 tHA tAW tPWE WE OE tSD DATA I/O tHD VALID DATA Write Cycle No. 3 (WE Controlled, OE LOW) [22] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD NOTE DATAI/O [21] tHD VALID DATA tLZWE tHZWE Truth Table CE1 CE2 WE OE H X X X High Z Inputs/Outputs Deselect/Power-down Mode Standby (ISB) Power X L X X High Z Deselect/Power-down Standby (ISB) L H H L Data Out (I/O0-I/O7) Read Active (ICC) L H H H High Z Output Disabled Active (Icc) L H L X Data in (I/O0-I/O7) Write Active (Icc) Notes: 20. Data I/O is high impedance if OE = VIH. 21. During this period, the I/Os are in output state and input signals should not be applied. 22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. Document #: 38-05391 Rev. *E Page 7 of 11 [+] Feedback CY62158DV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62158DV30L-45BVI Package Name BV48A Package Type Operating Range 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial Z-48 48 Pin TSOP I (Pb-free) Industrial ZS-44 44 Pin TSOP II (Pb-free) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial Z-48 48 Pin TSOP I (Pb-free) Industrial ZS-44 44 Pin TSOP II (Pb-free) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial Z-48 48 Pin TSOP I (Pb-free) Industrial ZS-44 44 Pin TSOP II (Pb-free) Industrial CY62158DV30LL-45BVI 45 CY62158DV30L-45ZXI CY62158DV30LL-45ZXI 45 CY62158DV30L-45ZSXI CY62158DV30LL-45ZSXI 55 CY62158DV30L-55BVI CY62158DV30LL-55BVI 55 CY62158DV30L-55ZXI CY62158DV30LL-55ZXI 55 CY62158DV30L-55ZSXI CY62158DV30LL-55ZSXI 70 CY62158DV30L-70BVI CY62158DV30LL-70BVI 70 CY62158DV30L-70ZXI CY62158DV30LL-70ZXI 70 CY62158DV30L-70ZSXI CY62158DV30LL-70ZSXI Document #: 38-05391 Rev. *E Page 8 of 11 [+] Feedback CY62158DV30 MoBL® Package Diagrams 48-lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B 48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. SEATING PLANE 0.004[0.10] 0.787[20.00] 0.004[0.10] 0.008[0.21] 0.010[0.25] GAUGE PLANE 0°-5° Document #: 38-05391 Rev. *E 0.020[0.50] 0.028[0.70] 51-85183-*A Page 9 of 11 [+] Feedback CY62158DV30 MoBL® Package Diagrams (continued) 44-pin TSOP II ZS44 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05391 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62158DV30 MoBL® Document History Page Document Title:CY62158DV30 MoBL® 8-Mbit (1024K x 8) MoBL® Static RAM Document Number: 38-05391 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 126293 05/22/03 HRT New Data Sheet *A 131014 11/25/03 CBD Change from Advance to Preliminary *B 133114 01/24/04 CBD Minor Change: MPN change and upload *C 211602 See ECN AJU Change from Preliminary to Final Changed Marketing part # from CY62158DV to CY62158DV30 in the “Title” and in the “Ordering Information” table Added footnote 4 and 10 Modified footnote 7 to include ramp time and wait time Removed MAX value for VDR on “Data Retention Characteristics” table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section *D 239450 See ECN SYT/AJU Added footnote #11 Added 45 ns and 70 ns Speed Bins *E 2897923 03/23/10 AJU Inactive parts; obsolete data sheet. Document #: 38-05391 Rev. *E Page 11 of 11 [+] Feedback