CY62158DV30L-55ZXI

CY62158DV30 MoBL 8-Mbit (1024K x 8) MoBL Static RAM Features • Very high speed: 45 ns, 55 ns and 70 ns — Wide voltage range: 2.20V – 3.60V • Ultra-low active power — Typical active current:1.5 mA @ f = 1 MHz — Typical active current: 12 mA @ f = fmax • Ultra-low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered in a 48-ball BGA, 48-pin TSOPI, and 44-pin TSOPII This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption by 85% when deselected (CE1 HIGH or CE2 LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). See the truth table for a complete description of read and write modes. Functional Description[1] The CY62158DV30 is a high-performance CMOS static RAMs organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE1 CE2 WE OE Data in Drivers I/O0 I/O1 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 1024K x 8 ARRAY COLUMN DECODER POWER DOWN I/O6 I/O7 Note: 1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com. A13 A14 A15 A16 A17 A18 A19 Cypress Semiconductor Corporation Document #: 38-05391 Rev. *D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 17, 2004 [+] [+] Feedback CY62158DV30 MoBL Pin Configuration[2, 3, 4] FBGA Top View 1 DNU 2 OE 3 A0 A3 A5 A17 DNU A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 6 CE2 A B C D E F G H DNU DNU I/O0 VSS VCC I/O3 DNU A18 A 48TSOPI A Top View DNU I/O1 I/O2 DNU NC A8 CE1 DNU DNU I/O5 I/O6 DNU WE A11 I/O4 VCC VSS I/O7 DNU A19 44 TSOPII Top View A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU DNU DNU A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss A19 I/O7 DNU I/O6 DNU I/O5 DNU I/O4 Vcc DNU I/O3 DNU I/O2 DNU I/O1 DNU I/O0 OE Vss CE1 A0 A4 A3 A2 A1 A0 CE1 DNU DNU I/O0 I/O1 VCC VSS I/O2 I/O3 DNU DNU WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CE2 A8 DNU DNU I/O7 I/O6 VSS VCC I/O5 I/O4 DNU DNU A9 A10 A11 A12 A13 A14 Notes: 2. NC pins are not internally connected to the die. 3. DNU pins have to be left floating. 4. The BYTE pin in the TSOPI package has to be tied LOW to use the device as 1M x 8 SRAM. The 48-TSOPI package can also be used as a 512K × 16 SRAM by tying the BYTE signal HIGH. For 512K x 16 functionality, please refer to the CY62157DV30 data sheet. Document #: 38-05391 Rev. *D Page 2 of 11 [+] [+] Feedback CY62158DV30 MoBL Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................... 55°C to +125°C Supply Voltage to Ground Potential .–0.3V to Vcc(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[5, 6] ......................... –0.3V to VCC(max) + 0.3V DC Input Voltage[5, 6] ..................... –0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Product CY62158DV30L CY62158DV30LL Range Ambient Temperature (TA) VCC[7] Industrial –40°C to +85°C 2.2V – 3.6V Product Portfolio Power Dissipation Operating ICC (mA) VCC Range (V) Product CY62158DV30L CY62158DV30LL Min. 2.2 2.2 Typ.[8] 3.0 3.0 Max. 3.6 3.6 Speed (ns) 45,55,70 45,55,70 f = 1 MHz Typ.[8] 1.5 1.5 Max. 3 3 f = fmax Typ.[8] 12 12 Max. 20 15 Standby ISB2(µA) Typ.[8] 2 2 Max. 20 8 Electrical Characteristics Over the Operating Range CY62158DV30 Parameter VOH VOL VIH VIIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1mA VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz ISB1 Automatic CE Power-down Current — CMOS Inputs Automatic CE Power-down Current — CMOS Inputs VCC = VCCmax L IOUT = 0 mA LL CMOS levels L LL CE1 > VCC− 0.2V, CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = 3.60V CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V L LL L LL 2 2 2 2 Test Conditions VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 –0.3 –0.3 –1 –1 12 1.5 Min. Typ.[8] 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 20 15 3 3 20 8 20 8 µA Max. Unit V V V V V V V V µA µA mA mA mA mA µA ISB2 Notes: 5. VIL(min.) = –2.0V for pulse durations less than 20 ns. 6. VIH(max)= VCC+0.75V for pulse duration less than 20ns. 7. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05391 Rev. *D Page 3 of 11 [+] [+] Feedback CY62158DV30 MoBL Capacitance[9, 10.] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Max. 10 10 Unit pF pF Thermal Resistance Parameter ΘJA ΘJC Description Thermal Resistance[9] (Junction to Ambient) Thermal Resistance[9] (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board BGA 72 8.86 TSOP II 75.13 8.95 TSOP I 74.88 8.6 Unit °C/W °C/W AC Test Loads and Waveforms [11] R1 VCC OUTPUT 30 pF / 50 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10% Fall time: 1 V/ns Rise Time: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH VTH OUTPUT Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 3.0V 1103 1554 645 1.75 Unit Ω Ω Ω V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[9] tR[12] Description VCC for Data Retention Data Retention Current VCC = 1.5V L CE1 > VCC − 0.2V or CE2 VCC − 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 10 4 Typ.[8] Max. Unit V µA µA ns ns Chip Deselect to Data Retention Time Operation Recovery Time Notes: 9. Tested initially and after any design or process changes that may affect these parameters. 10. The input capacitance on the CE2 pin is 15 pF. 11. Test condition for the 45 ns part is a load capacitance of 30 pF. 12. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05391 Rev. *D Page 4 of 11 [+] [+] Feedback CY62158DV30 MoBL Data Retention Waveform DATA RETENTION MODE VCC CE1 VCC(min) tCDR VDR > 1.5 V VCC(min) tR or CE2 Switching Characteristics Over the Operating Range [13] 45 ns [11] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[16] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[14, 15] [14] 55 ns Min. 55 Max. 70 ns Min. 70 55 70 10 55 25 70 35 5 20 25 10 20 25 10 55 25 70 60 60 0 0 45 30 0 20 25 10 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[14] Z[14, 15] Z[14] Min. 45 Max. 45 10 45 25 5 15 10 20 0 45 45 40 40 0 0 35 25 0 15 10 10 55 40 40 0 0 40 25 0 0 10 Z[14, 15] 5 10 OE HIGH to High CE1 LOW and CE2 HIGH to Low CE1 HIGH or CE2 LOW to High CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH or CE2 LOW to Power-Down WE HIGH to Low Z Notes: 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05391 Rev. *D Page 5 of 11 [+] [+] Feedback CY62158DV30 MoBL Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID [17, 18] tRC Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE tPU SUPPLY CURRENT 50% [16, 20, 22] tHZOE tHZCE DATA VALID tPD 50% HIGH IMPEDANCE ICC ISB Write Cycle No. 1(WE Controlled) tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE [20] tHZOE Notes: 17. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 18. WE is HIGH for read cycle. 19. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. tHD VALID DATA Document #: 38-05391 Rev. *D Page 6 of 11 [+] [+] Feedback CY62158DV30 MoBL Switching Waveforms (continued) Write Cycle No. 2(CE1 or CE2 Controlled) [16, 20, 22] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tHA OE tSD DATA I/O VALID DATA [22] tHD Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATA I/O NOTE [21] tHA tPWE tHD VALID DATA tHZWE tLZWE Truth Table CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X Inputs/Outputs High Z High Z Data Out (I/O0-I/O7) High Z Data in (I/O0-I/O7) Mode Deselect/Power-down Deselect/Power-down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (Icc) Active (Icc) Notes: 20. Data I/O is high impedance if OE = VIH. 21. During this period, the I/Os are in output state and input signals should not be applied. 22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. Document #: 38-05391 Rev. *D Page 7 of 11 [+] [+] Feedback CY62158DV30 MoBL Ordering Information Speed (ns) 45 45 45 55 55 55 70 70 70 Ordering Code CY62158DV30L-45BVI CY62158DV30LL-45BVI CY62158DV30L-45ZXI CY62158DV30LL-45ZXI CY62158DV30L-45ZSXI CY62158DV30LL-45ZSXI CY62158DV30L-55BVI CY62158DV30LL-55BVI CY62158DV30L-55ZXI CY62158DV30LL-55ZXI CY62158DV30L-55ZSXI CY62158DV30LL-55ZSXI CY62158DV30L-70BVI CY62158DV30LL-70BVI CY62158DV30L-70ZXI CY62158DV30LL-70ZXI CY62158DV30L-70ZSXI CY62158DV30LL-70ZSXI ZS-44 44 Pin TSOP II (Pb-free) Industrial Z-48 48 Pin TSOP I (Pb-free) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial ZS-44 44 Pin TSOP II (Pb-free) Industrial Z-48 48 Pin TSOP I (Pb-free) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial ZS-44 44 Pin TSOP II (Pb-free) Industrial Z-48 48 Pin TSOP I (Pb-free) Industrial Package Name BV48A Package Type 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Operating Range Industrial Document #: 38-05391 Rev. *D Page 8 of 11 [+] [+] Feedback CY62158DV30 MoBL Package Diagrams 48-lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B 48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142 MAX. 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE 0°-5° 0.002[0.05] 0.006[0.15] 51-85183-*A Document #: 38-05391 Rev. *D Page 9 of 11 [+] [+] Feedback CY62158DV30 MoBL Package Diagrams (continued) 44-pin TSOP II ZS44 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05391 Rev. *D Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY62158DV30 MoBL Document History Page Document Title:CY62158DV30 MoBL 8-Mbit (1024K x 8) MoBL Static RAM Document Number: 38-05391 REV. ** *A *B *C ECN NO. 126293 131014 133114 211602 Issue Date 05/22/03 11/25/03 01/24/04 See ECN Orig. of Change HRT CBD CBD AJU New Data Sheet Change from Advance to Preliminary Minor Change: MPN change and upload Change from Preliminary to Final Changed Marketing part # from CY62158DV to CY62158DV30 in the “Title” and in the “Ordering Information” table Added footnote 4 and 10 Modified footnote 7 to include ramp time and wait time Removed MAX value for VDR on “Data Retention Characteristics” table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section Added footnote #11 Added 45 ns and 70 ns Speed Bins Description of Change *D 239450 See ECN SYT/AJU Document #: 38-05391 Rev. *D Page 11 of 11 [+] [+] Feedback