CY62158E

CY62158E MoBL® 8-Mbit (1 M × 8) Static RAM 8-Mbit (1 M × 8) Static RAM Features ■ Very high speed: 45 ns ❐ Wide voltage range: 4.5 V–5.5 V Ultra low active power ❐ Typical active current:1.8 mA at f = 1 MHz ❐ Typical active current: 18 mA at f = fmax Ultra low standby power ❐ Typical standby current: 2 A ❐ Maximum standby current: 8 A Easy memory expansion with CE1, CE2 and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 44-pin TSOP II package ■ advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table on page 11 for a complete description of read and write modes. ■ ■ ■ ■ ■ Functional Description The CY62158E MoBL® is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features Logic Block Diagram CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 WE OE DATA IN DRIVERS ROW DECODER I/O IO00 I/O IO11 SENSE AMPS I/O IO22 I/O IO33 I/O IO44 I/O IO55 I/O IO66 I/O IO77 1024K x 8 ARRAY COLUMN DECODER POWER DOWN A15 A16 A17 A13 A14 A18 A19 Cypress Semiconductor Corporation Document #: 38-05684 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 10, 2011 [+] Feedback CY62158E MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Document #: 38-05684 Rev. *H Page 2 of 16 [+] Feedback CY62158E MoBL® Pin Configuration Figure 1. 44-pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE1 NC NC I/O0 I/O1 VCC VSS I/O2 I/O3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CE2 A8 NC NC I/O7 I/O6 VSS VCC I/O5 I/O4 NC NC A9 A10 A11 A12 A13 A14 Product Portfolio Power Dissipation Product VCC Range (V) Min CY62158ELL 4.5 Typ [2] 5.0 Max 5.5 45 Speed (ns) Typ [2] 1.8 Operating ICC (mA) f = 1 MHz Max 3 f = fmax Typ [2] 18 Max 25 Standby ISB2 (A) Typ [2] 2 Max 8 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05684 Rev. *H Page 3 of 16 [+] Feedback CY62158E MoBL® Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Supply Voltage to Ground Potential .......................... –0.5 V to VCC(max) + 0.5 V DC Voltage Applied to Outputs in High Z State [3, 4] ......................–0.5 V to VCC(max) + 0.5 V DC Input Voltage [3, 4] ..................–0.5 V to VCC(max) + 0.5 V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001 V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA Operating Range Device Range Ambient Temperature –40 °C to +85 °C VCC [5] 4.5 V–5.5 V CY62158ELL Industrial Electrical Characteristics Over the Operating Range -45 Parameter VOH VOL VIH VIIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power down Current — CMOS Inputs Test Conditions IOH = –1 mA IOL = 2.1 mA VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels Min 2.4 – 2.2 –0.5 –1 –1 – Typ [6] – – – – – – 18 1.8 – 2 Max – 0.4 VCC + 0.5 V 0.8 +1 +1 25 3 8 Unit V V V V A A mA mA A CE1 > VCC0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V, VIN < 0.2 V f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = VCCmax CE1 > VCC – 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCCmax ISB2 [7] Automatic CE Power-down Current — CMOS Inputs – 2 8 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05684 Rev. *H Page 4 of 16 [+] Feedback CY62158E MoBL® Capacitance Parameter [8] CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Parameter [8] JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 44-pin TSOP II Unit 75.13 8.95 C/W C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 3V 100 pF INCLUDING JIG AND SCOPE R2 GND 10% VCC OUTPUT ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 5.0 V 1838 994 645 1.75 Unit    V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05684 Rev. *H Page 5 of 16 [+] Feedback CY62158E MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR [10] Description VCC for Data Retention Data Retention Current Conditions VCC = VDR CE1 > VCC  0.2 V, CE2 < 0.2 V, VIN > VCC  0.2 V or VIN < 0.2 V Min 2 – Typ [9] – – Max – 8 Unit V A tCDR [11] tR [12] Chip Deselect to Data Retention Time Operation Recovery Time 0 45 – – – – ns ns Data Retention Waveform Figure 3. Data Retention Waveform VCC CE1 VCC(min) tCDR DATA RETENTION MODE VDR > 2.0 V VCC(min) tR or CE2 Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document #: 38-05684 Rev. *H Page 6 of 16 [+] Feedback CY62158E MoBL® Switching Characteristics Over the Operating Range Parameter [13] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle [16] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z [14, 15] [14] Description 45 ns Min 45 – 10 – – 5 – 10 – 0 – 45 35 35 0 0 35 25 0 – 10 Max – 45 – 45 22 – 18 – 18 – 45 – – – – – – – – 18 – Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z [14] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High Z [14, 15] CE1 LOW and CE2 HIGH to Low Z [14] CE1 HIGH or CE2 LOW to High Z [14, 15] CE1 LOW and CE2 HIGH to Power Up CE1 HIGH or CE2 LOW to Power Down Notes 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05684 Rev. *H Page 7 of 16 [+] Feedback CY62158E MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [17, 18] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 17. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 18. WE is HIGH for read cycle. 19. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 38-05684 Rev. *H Page 8 of 16 [+] Feedback CY62158E MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled) [20, 21, 22] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 23 tHZOE VALID DATA tHD Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [20, 21, 22] tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA OE tSD DATA I/O VALID DATA tHD Notes 20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. Data I/O is high impedance if OE = VIH. 22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 23. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05684 Rev. *H Page 9 of 16 [+] Feedback CY62158E MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [24] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATA I/O NOTE 25 tHZWE VALID DATA tLZWE tHD tPWE tHA Notes 24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05684 Rev. *H Page 10 of 16 [+] Feedback CY62158E MoBL® Truth Table CE1 H X [26] CE2 X [26] WE X X H H L OE X X L H X High Z High Z Inputs/Outputs Mode Deselect/Power Down Deselect/Power Down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) L H H H L L L Data Out High Z Data in Note 26. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 38-05684 Rev. *H Page 11 of 16 [+] Feedback CY62158E MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62158ELL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85087 44-pin TSOP II (Pb-free) Contact your local Cypress sales representative for availability of this part. Ordering Code Definitions CY 621 5 8 E LL - 45 ZS X I Temperature Grade: I = Industrial Pb-free Package Type: ZS = 44-pin TSOP II Speed Grade: 45 ns LL = Low Power Process Technology: 90 nm Bus width = × 8 Density = 8-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 38-05684 Rev. *H Page 12 of 16 [+] Feedback CY62158E MoBL® Package Diagrams Figure 9. 44-pin TSOP Z44-II, 51-85087 22 1 PIN 1 I.D. 11.938 (0.470) 11.735 (0.462) 10.262 (0.404) 10.058 (0.396) ZZZ ZXZ AA 23 44 TOP VIEW BOTTOM VIEW EJECTOR MARK (OPTIONAL) CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG 0.800 BSC (0.0315) 0.400(0.016) 0.300 (0.012) BASE PLANE 10.262 (0.404) 10.058 (0.396) 0.10 (.004) 18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE 0°-5° 0.210 (0.0083) 0.120 (0.0047) 0.597 (0.0235) 0.406 (0.0160) DIMENSION IN MM (INCH) MAX MIN. 51-85087 *C Document #: 38-05684 Rev. *H Page 13 of 16 [+] Feedback CY62158E MoBL® Acronyms Acronym CE CMOS I/O OE SRAM TSOP WE chip enable complementary metal oxide semiconductor input/output output enable static random access memory thin small outline package write enable Description Document Conventions Units of Measure Symbol °C MHz A s mA ns  % pF V W degree Celsius Mega Hertz micro Amperes micro seconds milli Amperes nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document #: 38-05684 Rev. *H Page 14 of 16 [+] Feedback CY62158E MoBL® Document History Page Document Title: CY62158E MoBL®, 8-Mbit (1 M × 8) Static RAM Document Number: 38-05684 REV. ** *A ECN NO. Issue Date 270350 291271 See ECN See ECN Orig. of Change PCI SYT Description of Change New Data Sheet Converted from Advance Information to Preliminary Changed input pulse level from VCC to 3V in the AC Test Loads and Waveforms Modified footnote #9 to include timing reference level of 1.5V and input pulse level of 3V *B 1462592 See ECN VKN/AESA Converted from preliminary to final Removed 35 ns speed bin Removed “L” parts Removed 48-Ball VFBGA package Changed ICC(max) spec from 2.3 mA to 3 mA at f=1 MHz Changed ICC(typ) spec from 16 mA to 18 mA at f=fMAX Changed ICC(max) spec from 28 mA to 25 mA at f=fMAX Changed ISB1(typ) and ISB2(typ) spec from 0.9 A to 2 A Changed ISB1(max) and ISB2(max) spec from 4.5 A to 8 A Changed ICCDR(max) spec from 4.5 A to 8 A Changed tLZOE spec from 3 ns to 5 ns Changed tLZCE spec from 6 ns to 10 ns Changed tHZCE spec from 22 ns to 18 ns Changed tPWE spec from 30 ns to 35 ns Changed tSD spec from 22 ns to 25 ns Changed tLZWE spec from 6 ns to 10 ns Added footnote# 6 related to ISB2 and ICCDR Updated Ordering information table See ECN VKN/PYRS Corrected typo in the Ordering Information table See ECN 06/03/10 PYRS VKN Corrected ECN number Added footnote #19 related to chip enable Updated package diagram Updated template Updated Logic Block Diagram. Added Ordering Code Definitions. Updated the missing header and footer in Pg 12. Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines”). Updated Data Retention Characteristics. Added Acronyms and Units of Measure. Updated in new template. *C *D *E 2428708 2516494 2934396 *F *G *H 3110202 3121955 3279426 12/14/2010 12/28/2010 06/10/2011 PRAS SRIH RAME Document #: 38-05684 Rev. *H Page 15 of 16 [+] Feedback CY62158E MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05684 Rev. *H Revised June 10, 2011 Page 16 of 16 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback