CY62158EV30

CY62158EV30 MoBL® 8-Mbit (1024 K × 8) Static RAM 8-Mbit (1024 K × 8) Static RAM Features ■ Functional Description The CY62158EV30 is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. See Truth Table on page 10 for a complete description of read and write modes. Very high speed: 45 ns ❐ Wide voltage range: 2.20 V–3.60 V Pin compatible with CY62158DV30 Ultra low standby power ❐ Typical standby current: 2 A ❐ Maximum standby current: 8 A Ultra low active power ❐ Typical active current: 1.8 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II packages ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Cypress Semiconductor Corporation Document #: 38-05578 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 30, 2011 [+] Feedback CY62158EV30 MoBL® Contents Pin Configurations ...........................................................3 Product Portfolio ..............................................................3 Maximum Ratings .............................................................4 Operating Range ...............................................................4 Electrical Characteristics .................................................4 Capacitance ......................................................................5 Thermal Resistance ..........................................................5 AC Test Loads and Waveforms .......................................5 Data Retention Characteristics .......................................6 Data Retention Waveform ................................................6 Switching Characteristics ................................................7 Switching Waveforms ......................................................8 Read Cycle No. 1 (Address Transition Controlled) .....8 Read Cycle No. 2 (OE Controlled) ..............................8 Write Cycle No. 1 (WE Controlled) ..............................9 Write Cycle No. 2 (CE1 or CE2 Controlled) .................9 Write Cycle No. 3 (WE Controlled, OE LOW) ............10 Truth Table ......................................................................10 Ordering Information ......................................................11 Ordering Code Definitions .........................................11 Package Diagrams ..........................................................12 Acronyms ........................................................................14 Document Conventions .................................................14 Units of Measure .......................................................14 Document History Page .................................................15 Sales, Solutions, and Legal Information ......................16 Worldwide Sales and Design Support .......................16 Products ....................................................................16 PSoC Solutions .........................................................16 Document #: 38-05578 Rev. *G Page 2 of 16 [+] Feedback CY62158EV30 MoBL® Pin Configurations [1] 48-ball VFBGA Top View 1 NC NC I/O0 VSS VCC I/O3 NC A18 2 OE NC NC I/O1 I/O2 NC NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 NC I/O5 I/O6 NC WE A11 6 CE2 NC I/O4 VCC VSS I/O7 NC A19 A B C D E F G H A4 A3 A2 A1 A0 CE1 NC NC I/O0 I/O1 VCC VSS I/O2 I/O3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin TSOP II Top View A5 A6 A7 OE CE2 A8 NC NC I/O7 I/O6 VSS VCC I/O5 I/O4 NC NC A9 A10 A11 A12 A13 A14 Product Portfolio Power Dissipation Product Min CY62158EV30LL 2.2 VCC Range (V) Typ[2] 3.0 Max 3.6 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ[2] 1.8 Max 3 f = fmax Typ[2] 18 Max 25 Standby, ISB2 (μA) Typ[2] 2 Max 8 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05578 Rev. *G Page 3 of 16 [+] Feedback CY62158EV30 MoBL® Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature .............................. –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Supply Voltage to Ground Potential ..........................–0.3 V to VCC(max) + 0.3 V DC Voltage Applied to Outputs in High Z State[3, 4] ..................... –0.3 V to VCC(max) + 0.3 V DC Input Voltage[3, 4] .................. –0.3 V to VCC(max) + 0.3 V Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage ........................................> 2001 V (MIL-STD-883, Method 3015) Latch up Current ....................................................> 200 mA Operating Range Product CY62158EV30LL Range Industrial Ambient Temperature (TA) VCC[5] –40 °C to +85 °C 2.2 V–3.6 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = –0.1 mA IOH = –1.0 mA, VCC > 2.70 V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70 V VCC = 2.2 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.2 V to 2.7 V VCC = 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, Output Disabled f = 1 MHz ISB1 Automatic CE Power down Current — CMOS Inputs VCC = VCCmax IOUT = 0 mA CMOS levels 45 ns Min 2.0 2.4 – – 1.8 2.2 –0.3 –0.3 –1 –1 – – – Typ[6] – – – – – – – – – – 18 1.8 2 Max – – 0.4 0.4 VCC + 0.3 V VCC + 0.3 V 0.6 0.8 +1 +1 25 3 8 Unit V V V V V V V V A A mA mA A VCC Operating Supply Current f = fmax = 1/tRC CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60 V CE1 > VCC – 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V ISB2[7] Automatic CE Power down Current — CMOS Inputs – 2 8 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max)= VCC + 0.75 V for pulse duration less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05578 Rev. *G Page 4 of 16 [+] Feedback CY62158EV30 MoBL® Capacitance Parameter[8] CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Parameter[8] JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 48-ball BGA 44-pin TSOP II Unit 72 8.86 76.88 13.52 C/W C/W AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10% Rise Time: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH VTH Fall time: 1 V/ns OUTPUT Parameters R1 R2 RTH VTH 2.5 V 16667 15385 8000 1.20 3.0 V 1103 1554 645 1.75 Unit    V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05578 Rev. *G Page 5 of 16 [+] Feedback CY62158EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR [10] Description VCC for Data Retention Data Retention Current Conditions VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Min 1.5 – Typ[9] – 2 Max – 5 Unit V A tCDR[11] tR [12] Chip Deselect to Data Retention Time Operation Recovery Time 0 45 – – – – ns ns Data Retention Waveform VCC CE1 VCC, min tCDR DATA RETENTI/ON MODE VDR > 1.5 V VCC, min tR or CE2 Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document #: 38-05578 Rev. *G Page 6 of 16 [+] Feedback CY62158EV30 MoBL® Switching Characteristics Over the Operating Range Parameter[13] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[14] OE HIGH to High Z[14, 15] CE1 LOW and CE2 HIGH to Low Z[14] CE1 HIGH or CE2 LOW to High Z[14, 15] CE1 LOW and CE2 HIGH to Power Up CE1 HIGH or CE2 LOW to Power Down Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High WE HIGH to Low Z[14, 15] Z[14] 45 – 10 – – 5 – 10 – 0 – 45 35 35 0 0 35 25 0 – 10 – 45 – 45 22 – 18 – 18 – 45 – – – – – – – – 18 – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description 45 ns Min Max Unit Write Cycle[16] Notes 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05578 Rev. *G Page 7 of 16 [+] Feedback CY62158EV30 MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[17, 18] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled)[18, 19] ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 17. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 18. WE is HIGH for read cycle. 19. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 38-05578 Rev. *G Page 8 of 16 [+] Feedback CY62158EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[20, 21, 22] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 23 tHZOE VALID DATA tHD Write Cycle No. 2 (CE1 or CE2 Controlled)[20, 21, 22] tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA OE tSD DATA I/O VALID DATA tHD Notes 20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. Data I/O is high impedance if OE = VIH. 22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 23. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05578 Rev. *G Page 9 of 16 [+] Feedback CY62158EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[24] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATA I/O NOTE 25 tHZWE VALID DATA tLZWE tHD tPWE tHA Truth Table CE1 H X [26] CE2 X [26] WE X X H L H OE X X L X H Inputs/Outputs High Z High Z Data Out Data In High Z Mode Deselect/Power down Deselect/Power down Read Write Selected, Outputs Disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) L H H H L L L Notes 24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. 26. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 38-05578 Rev. *G Page 10 of 16 [+] Feedback CY62158EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62158EV30LL-45BVXI CY62158EV30LL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85150 48-ball Very Fine-Pitch Ball Grid Array (Pb-free) 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 5 8 E V30 LL - 45 XX X I Temperature Grade: I = Industrial Pb-free Package Type: XX = BV or ZS BV = 48-ball VFBGA ZS = 44-pin TSOP II Speed Grade = 45 ns LL = Low Power Voltage Range = 3 V typical E = Process Technology 90 nm Buswidth = × 8 Density = 8-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 38-05578 Rev. *G Page 11 of 16 [+] Feedback CY62158EV30 MoBL® Package Diagrams Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150 51-85150 *F Document #: 38-05578 Rev. *G Page 12 of 16 [+] Feedback CY62158EV30 MoBL® Package Diagrams (continued) Figure 2. 44-pin TSOP Z44-II, 51-85087 51-85087 *C Document #: 38-05578 Rev. *G Page 13 of 16 [+] Feedback CY62158EV30 MoBL® Acronyms Acronym CE CMOS I/O OE RAM SRAM TTL TSOP VFBGA WE chip enable complementary metal oxide semiconductor input/output output enable random access memory static random access memory transistor-transistor logic thin small outline package very fine-pitch ball grid array write enable Description Document Conventions Units of Measure Symbol °C MHz μA μs mA mm ns  % pF V W degree Celcius Mega Hertz micro Amperes micro seconds milli Amperes milli meter nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document #: 38-05578 Rev. *G Page 14 of 16 [+] Feedback CY62158EV30 MoBL® Document History Page Document Title: CY62158EV30 MoBL®, 8-Mbit (1024 K × 8) Static RAM Document Number: 38-05578 Rev. ** *A *B ECN No. 270329 291271 444306 Issue Date See ECN See ECN See ECN Orig. of Change PCI SYT NXR New Data Sheet Converted from Advance Information to Preliminary Changed ICCDR from 4 to 4.5 A Converted from Preliminary to Final. Removed 35 ns speed bin Removed “L” bin. Removed 44 pin TSOP II package Included 48 pin TSOP I package Changed the ICC Typ value from 16 mA to 18 mA and ICC max value from 28 mA to 25 mA for test condition f = fax = 1/tRC. Changed the ICC max value from 2.3 mA to 3 mA for test condition f = 1MHz. Changed the ISB1 and ISB2 max value from 4.5 A to 8 A and Typ value from 0.9 A to 2 A respectively. Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF. Added Typ value for ICCDR . Changed the ICCDR max value from 4.5 A to 5 A Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tLZOE from 3 to 5 Changed tLZCE from 6 to 10 Changed tHZCE from 22 to 18 Changed tPWE from 30 to 35 Changed tSD from 22 to 25 Changed tLZWE from 6 to 10 Updated the ordering Information and replaced the Package Name column with Package Diagram. Included 44 pin TSOP II package in Product Offering. Removed TSOP I package; Added reference to CY62157EV30 TSOP I Updated the ordering Information table Added footnote #8 related to ISB2 and ICCDR Added footnote #21 related to chip enable Updated package diagrams Updated template Updated Logic Block Diagram and Package Diagram. Added Ordering Code Definitions. Updated Features. Removed the note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.” and its reference in Functional Description. Updated Data Retention Characteristics. Added Acronyms and Units of Measure. Updated in new template. Description of Change *C 467052 See ECN NXR *D *E 1015643 2934396 See ECN 06/03/10 VKN VKN *F *G 3110202 3269641 12/14/2010 05/30/2011 PRAS RAME Document #: 38-05578 Rev. *G Page 15 of 16 [+] Feedback CY62158EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05578 Rev. *G Revised May 30, 2011 Page 16 of 16 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback