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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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www.infineon.com
CY62158EV30 MoBL
8-Mbit (1024K × 8) Static RAM
8-Mbit (1024K × 8) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
❐ Wide voltage range: 2.20 V–3.60 V
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE1 HIGH or
CE2 LOW). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE1 HIGH or CE2 LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE1 LOW and
CE2 HIGH and WE LOW).
■
Pin compatible with CY62158DV30
■
Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A
■
Ultra low active power
❐ Typical active current: 6 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed/power
■
Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the I/O pins. See Truth Table on page 11
for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
1024K x 8
ARRAY
SENSE AMPS
ROW DECODER
I/O1
IO
1
I/O2
IO
2
I/O3
IO
3
I/O
IO
44
I/O
IO
55
I/O6
IO
6
COLUMN DECODER
WE
I/O
IO
77
POWER
DOWN
A15
A16
A17
A13
A14
OE
Cypress Semiconductor Corporation
Document Number: 38-05578 Rev. *M
I/O
IO
00
DATA IN DRIVERS
•
A18
A19
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 28, 2020
CY62158EV30 MoBL
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 38-05578 Rev. *M
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY62158EV30 MoBL
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1]
1
2
3
4
5
Figure 2. 44-pin TSOPpII pinout (Top View) [1]
6
NC
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
NC
A16
I/O6
VSS
E
I/O3
NC
A14
A15
NC
I/O7
F
NC
NC
A12
A13
WE
NC
G
A8
A9
A10
A11
A19
A18
A4
A3
A2
A1
A0
CE1
NC
NC
I/O0
I/O1
VCC
VSS
I/O2
I/O3
NC
NC
WE
A19
A18
A17
A16
A15
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
CE2
A8
NC
NC
I/O7
I/O6
VSS
VCC
I/O5
I/O4
NC
NC
A9
A10
A11
A12
A13
A14
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62158EV30LL
Operating ICC (mA)
Speed
(ns)
Min
Typ[2]
Max
2.2
3.0
3.6
45
f = 1 MHz
Standby, ISB2 (µA)
f = fmax
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
6
7
18
25
2
8
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05578 Rev. *M
Page 3 of 19
CY62158EV30 MoBL
DC Input Voltage [3, 4] ..................–0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Storage Temperature ............................... –65 °C to +150 °C
Latch up Current .................................................... > 200 mA
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Operating Range
Supply Voltage
to Ground Potential [3, 4] .............. –0.3 V to VCC(max) + 0.3 V
DC Voltage Applied to Outputs
in High Z State [3, 4] ......................–0.3 V to VCC(max) + 0.3 V
Product
Range
CY62158EV30LL
Industrial
Ambient
Temperature
(TA)
VCC[5]
–40 °C to +85 °C 2.2 V–3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output HIGH voltage
Test Conditions
45 ns
Unit
Min
Typ [6]
Max
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
–
–
0.4
V
VOL
Output LOW voltage
IOL = 0.1 mA
–
–
0.4
V
VIH
Input HIGH voltage
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3 V
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3 V
V
–
0.6
V
IOL = 2.1 mA, VCC > 2.70 V
VIIL
Input LOW voltage
VCC = 2.2 V to 2.7 V
–0.3
VCC = 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
–
18
25
mA
–
6
7
mA
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
ISB1
Automatic CE power down
current — CMOS Inputs
CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
–
2
8
A
ISB2[7]
Automatic CE Power down
Current — CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
2
8
A
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max)= VCC + 0.75 V for pulse duration less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2/ICCDR spec. Other inputs can be left floating.
Document Number: 38-05578 Rev. *M
Page 4 of 19
CY62158EV30 MoBL
Capacitance
Parameter [8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [8]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball BGA
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
44-pin TSOP II Unit
36.92
65.91
C/W
13.55
13.96
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
GND
30 pF
R2
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05578 Rev. *M
Page 5 of 19
CY62158EV30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ[9]
Max
Unit
1.5
–
–
V
–
3.2
8
A
VDR
VCC for data retention
ICCDR[10]
Data retention current
tCDR[11]
Chip deselect to data retention time
0
–
–
ns
Operation recovery time
45
–
–
ns
tR
[12]
VCC = 1.5 V, CE1 > VCC 0.2 V
or CE2 < 0.2 V, VIN > VCC 0.2 V
or VIN < 0.2 V
Data Retention Waveform
Figure 4. Data Retention Waveform
VCC
VCC, min
tCDR
DATA RETENTI/ON MODE
VDR > 1.5 V
VCC, min
tR
CE1
or
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2/ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 38-05578 Rev. *M
Page 6 of 19
CY62158EV30 MoBL
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data Hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low Z[15]
5
–
ns
tHZOE
tLZCE
OE HIGH to High
Z[15, 16]
–
18
ns
Z[15]
10
–
ns
Z[15, 16]
–
CE1 LOW and CE2 HIGH to Low
tHZCE
CE1 HIGH or CE2 LOW to High
18
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
0
–
ns
CE1 HIGH or CE2 LOW to Power Down
–
45
ns
tPD
Write Cycle
[17, 18]
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
–
ns
tAW
Address setup to Write End
35
–
ns
tHA
Address Hold from Write End
0
–
ns
ns
tSA
Address setup to Write Start
0
–
tPWE
WE pulse width
35
–
ns
tSD
Data setup to Write End
25
–
ns
tHD
Data Hold from Write End
0
–
ns
Z[15, 16]
–
18
ns
10
–
ns
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z[15]
Notes
13. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 3 on page 5.
15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
16. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
18. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05578 Rev. *M
Page 7 of 19
CY62158EV30 MoBL
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [19, 20]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [20, 21]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
50%
ICC
ISB
Notes
19. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
Document Number: 38-05578 Rev. *M
Page 8 of 19
CY62158EV30 MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [22, 23, 24]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 25
tHZOE
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled) [22, 23, 24]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tHA
tAW
tPWE
WE
OE
tSD
DATA I/O
tHD
VALID DATA
Notes
22. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
23. Data I/O is high impedance if OE = VIH.
24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05578 Rev. *M
Page 9 of 19
CY62158EV30 MoBL
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [26, 28]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 27
tHD
VALID DATA
tHZWE
tLZWE
Notes
26. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
28. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 38-05578 Rev. *M
Page 10 of 19
CY62158EV30 MoBL
Truth Table
CE1
WE
OE
[29]
X
X
High Z
Deselect/Power down
Standby (ISB)
X[29]
L
X
X
High Z
Deselect/Power down
Standby (ISB)
L
H
H
L
Data Out
Read
Active (ICC)
L
H
L
X
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
H
CE2
X
Inputs/Outputs
Mode
Power
Note
29. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05578 Rev. *M
Page 11 of 19
CY62158EV30 MoBL
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62158EV30LL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
CY62158EV30LL-45ZSXI
51-85087 44-pin TSOP Type II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 5
8
E V30 LL - 45 XX X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade = 45 ns
LL = Low Power
Voltage Range: V30 = 3 V typical
E = Process Technology 90 nm
Buswidth: 8 = × 8
Density: 5 = 8-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05578 Rev. *M
Page 12 of 19
CY62158EV30 MoBL
Package Diagrams
Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *I
Document Number: 38-05578 Rev. *M
Page 13 of 19
CY62158EV30 MoBL
Package Diagrams (continued)
Figure 11. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05578 Rev. *M
Page 14 of 19
CY62158EV30 MoBL
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
µA
microampere
RAM
Random Access Memory
µs
microsecond
SRAM
Static Random Access Memory
mA
milliampere
mm
millimeter
TTL
Transistor-Transistor Logic
TSOP
Thin Small Outline Package
VFBGA
Very Fine-Pitch Ball Grid Array
WE
Write Enable
Document Number: 38-05578 Rev. *M
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 15 of 19
CY62158EV30 MoBL
Document History Page
Document Title: CY62158EV30 MoBL, 8-Mbit (1024K × 8) Static RAM
Document Number: 38-05578
Rev.
ECN No.
Submission
Date
**
270329
09/28/2004
New data sheet.
*A
291271
11/19/2004
Changed status from Advance Information to Preliminary.
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 4 µA to 4.5 µA.
*B
444306
04/13/2006
Converted from Preliminary to Final.
Removed 35 ns Speed Bin related information in all instances across the document.
Removed 44-pin TSOP II Package related information in all instances across the document.
Included 48-pin TSOP I Package related information in all instances across the document.
Removed “L” from the part numbers across the document.
Updated Product Portfolio:
Changed maximum value of “Operating ICC” from 2.3 mA to 3 mA corresponding to
“f = 1 MHz”.
Changed typical value of “Operating ICC” from 16 mA to 18 mA corresponding to “f = fmax”.
Changed maximum value of “Operating ICC” from 28 mA to 25 mA corresponding to
“f = fmax”.
Changed typical value of “Standby ISB2” from 0.9 µA to 2 µA.
Changed maximum value of “Standby ISB2” from 4.5 µA to 8 µA.
Updated Electrical Characteristics:
Changed typical value of ISB1 parameter from 0.9 µA to 2 µA.
Changed maximum value of ISB1 parameter from 4.5 µA to 8 µA.
Changed typical value of ISB2 parameter from 0.9 µA to 2 µA.
Changed maximum value of ISB2 parameter from 4.5 µA to 8 µA.
Updated AC Test Loads and Waveforms:
Updated Figure 3 (Changed Test Load Capacitance from 50 pF to 30 pF).
Updated Data Retention Characteristics:
Added 2 µA as typical value for ICCDR parameter.
Changed maximum value of ICCDR parameter from 4.5 A to 5 A.
Changed minimum value of tR parameter from 100 s to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZCE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns corresponding to 45 ns
speed bin.
Changed minimum value of tPWE parameter from 30 ns to 35 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSD parameter from 22 ns to 25 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZWE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *B to *D.
Removed spec 51-85087 *A.
Added spec 51-85183 *A.
Updated to new template.
Document Number: 38-05578 Rev. *M
Description of Change
Page 16 of 19
CY62158EV30 MoBL
Document History Page (continued)
Document Title: CY62158EV30 MoBL, 8-Mbit (1024K × 8) Static RAM
Document Number: 38-05578
Rev.
ECN No.
Submission
Date
Description of Change
*C
467052
06/06/2006
Included 44-pin TSOP II Package related information in all instances across the document.
Updated Features:
Added Note “For 48-pin TSOP I pin configuration and ordering information, please refer to
CY62157EV30 Data sheet.” and referred the same note in 48-pin TSOP I package.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Removed spec 51-85183 *A.
Added spec 51-85087 *A,
*D
1015643
04/28/2007
Updated Electrical Characteristics:
Added Note 7 and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Added Note 10 and referred the same note in ICCDR parameter.
*E
2934396
06/03/2010
Updated Truth Table:
Added Note 29 and referred the same note in “X” under CE1 and CE2 columns.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *A to *C.
Updated to new template.
*F
3110202
12/14/2010
Updated Logic Block Diagram.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *E to *F.
*G
3269641
05/30/2011
Removed 48-pin TSOP I Package related information in all instances across the document.
Updated Functional Description:
Removed the note “For best practice recommendations, refer to the Cypress application
note “System Design Guidelines” at http://www.cypress.com.” and its reference.
Updated Data Retention Characteristics:
Changed minimum value of tR parameter from tRC ns to 45 ns.
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*H
3598409
04/24/2012
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *G.
spec 51-85087 – Changed revision from *C to *D.
Completing Sunset Review.
*I
4100078
08/20/2013
Updated Switching Characteristics:
Added Note 13 and referred the same note in “Parameter” column.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
*J
4576526
11/21/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 18 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 28 and referred the same note in Figure 9.
Document Number: 38-05578 Rev. *M
Page 17 of 19
CY62158EV30 MoBL
Document History Page (continued)
Document Title: CY62158EV30 MoBL, 8-Mbit (1024K × 8) Static RAM
Document Number: 38-05578
Rev.
ECN No.
Submission
Date
*K
4790694
06/08/2015
Updated Maximum Ratings:
Referred Notes 3, 4 in “Supply Voltage to Ground Potential”.
Updated to new template.
Completing Sunset Review.
Description of Change
*L
5979591
11/29/2017
Updated Cypress Logo and Copyright.
*M
6819908
02/28/2020
Updated Features:
Updated description.
Updated Product Portfolio:
Updated all values of “Operating ICC” corresponding to “f = 1 MHz”.
Updated Electrical Characteristics:
Updated all values of ICC parameter corresponding to “45 ns” and “f = 1 MHz”.
Updated Thermal Resistance:
Updated all values of JA, JC parameters corresponding to all packages.
Updated Data Retention Characteristics:
Updated all values of ICCDR parameter.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
Document Number: 38-05578 Rev. *M
Page 18 of 19
CY62158EV30 MoBL
Sales, Solutions, and Legal Information
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cypress.com/support
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cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
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and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05578 Rev. *M
Revised February 28, 2020
Page 19 of 19
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