CY62158G30-45ZSXI

CY62158G/CY62158GE MoBL 8-Mbit (1M × 8-bits) Static RAM with Error-Correcting Code (ECC) CY62158G/CY62158GE MoBL, 8-Mbit (1M × 8-bits) Static RAM with Error-Correcting Code (ECC) Features ■ Functional Description Ultra-low standby power ❐ Typical standby current: 1.4 µA ❐ Maximum standby current: 6.5 µA CY62158G/CY62158GE is a high-performance CMOS low-power (MoBL) SRAM device with embedded ECC. Device is accessed by asserting both chip enable inputs – CE1 as LOW and CE2 as HIGH. ■ High speed: 45 ns ■ Embedded error-correcting code (ECC) for single-bit error correction[1, 2] ■ Operating voltage range: 2.2 V to 3.6 V ■ 1.0-V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Available in Pb-free 48-ball VFBGA and 44-pin TSOP II package Write to the device is performed by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). Read from the device is performed by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table – CY62158G/CY62158GE on page 13 for a complete description of read and write modes. Product Portfolio Power Dissipation Product Features and Options (see Pin Configurations – CY62158G) CY62158G/CY62158GE Dual Chip Enable Range VCC Range Speed (V) (ns) Industrial 2.2 V–3.6 V 45 Operating ICC (mA) Standby ISB2 (µA) f = fmax Typ[3] Max Typ[3] Max 18 25 1.4 6.5 Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate 2001 V Latch-up current ..................................................... >140 mA Operating Range Supply voltage to ground potential ..... –0.5 V to VCC + 0.5 V DC voltage applied to outputs in High Z state[7] .................................. –0.5 V to VCC + 0.5 V Grade Ambient Temperature VCC[8] Industrial –40 °C to +85 °C 2.2 V to 3.6 V DC Electrical Characteristics Over the Operating Range of –40 °C to 85 °C Parameter Description 45 ns Test Conditions Min Typ[9] Max Unit 4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.4[10] – – Output LOW voltage 4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4 V VIH[7] Input HIGH voltage 4.5 V to 5.5 V – 2.2 – VCC + 0.5 V VIL[7] Input LOW voltage 4.5 V to 5.5 V – –0.5 – 0.8 V IIX Input leakage current GND < VIN < VCC –1.0 – +1.0 µA IOZ Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 µA ICC VCC operating supply current f = 22.22 MHz VCC = Max, IOUT = 0 mA, (45 ns) CMOS levels f = 1 MHz – 18.0 25.0 – 6.0 7.0 – 1.4 6.5 25 °C[12] – 1.4 2.8 40 °C[12] – 3.5 [12] 70 °C – 5.5 85 °C – 6.5 VOH Output HIGH voltage VOL ISB1[11] CE1 > VCC – 0.2 V or CE2 < 0.2 V, Automatic power down current – VIN > VCC – 0.2 V, VIN < 0.2 V, CMOS inputs; f = fmax (address and data only), VCC = 2.2 to 3.6 V f = 0 (OE, and WE), VCC = VCC(max) ISB2[11] CE1 > VCC – 0.2 V or Automatic power down current – CE2 < 0.2 V, or CMOS inputs; VIN > VCC – 0.2 V or VCC = 2.2 to 3.6 V VIN < 0.2 V, f = 0, VCC = VCC(max) V mA µA µA Notes 7. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 8. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = 3V (for VCC range of 2.2 V to 3.6 V), TA = 25 °C. 10. This parameter is guaranteed by design and not tested. 11. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 12. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested. Document Number: 002-29691 Rev. *A Page 6 of 19 CY62158G/CY62158GE MoBL Capacitance Parameter[13] Description CIN Input capacitance COUT Output capacitance Test Conditions Max TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Unit 10 pF 10 pF Thermal Resistance Parameter[13] Description ΘJA Thermal resistance (junction to ambient) ΘJC Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 48-ball VFBGA 44-pin TSOP II Unit 36.92 66.93 °C/W 13.55 13.09 °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms VCC OUTPUT R1 VHIGH GND 30 pF R2 10% ALL INPUT PULSES 90% 90% 10% Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 5.0 V Unit R1 1800 Ω R2 990 Ω RTH 639 Ω VTH 1.77 V VHIGH 5.0 V Note 13. Tested initially and after any design or process changes that may affect these parameters. Document Number: 002-29691 Rev. *A Page 7 of 19 CY62158G/CY62158GE MoBL Data Retention Characteristics Over the Operating Range Parameter VDR Description Conditions VCC for data retention ICCDR[14, 15] Data retention current Min Typ[14] Max Unit 1.0 – – V 4 9 3.2 8 Vcc = 1.2V CE1 > VCC − 0.2 V or CE2 < 0.2 V, Vcc = 1.5V VIN > VCC − 0.2 V or 2.2 V < VCC < 3.6 V VIN < 0.2 V – 1.4 6.5 µA tCDR[16] Chip deselect to data retention time – 0 – – – tR[16, 17] Operation recovery time – 45 – – ns Data Retention Waveform Figure 5. Data Retention Waveform V CC V C C (m in ) tCDR D A T A R E T E N T IO N M O D E V D R = 1 .0 V V C C (m in ) tR CE1 (o r) CE2 Notes 14. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V), TA = 25 °C. 15. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. ICCDR is guaranteed only after device is first powered up to VCC(min) and brought down to VDR. 16. These parameters are guaranteed by design. 17. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document Number: 002-29691 Rev. *A Page 8 of 19 CY62158G/CY62158GE MoBL Switching Characteristics Parameter[18] Description 45 ns Unit Min Max 45.0 – ns – 45.0 ns Read Cycle tRC Read cycle time tAA Address to data valid tOHA Data hold from address change 10.0 – ns tACE CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid – 45.0 ns tDOE OE LOW to data valid / OE LOW to ERR valid – 22.0 ns 5.0 – ns tLZOE OE LOW to Low Z[19, 20, 21] Z[19, 20, 21, 22] tHZOE OE HIGH to High tLZCE CE1 LOW and CE2 HIGH to Low Z[19, 20, 21] tHZCE tPU tPD CE1 HIGH and CE2 LOW to High Z[19, 20, 21, 22] – 18.0 ns 10.0 – ns – 18.0 ns CE1 LOW and CE2 HIGH to power-up[21] 0 – ns CE1 HIGH and CE2 LOW to power-down[21] – 45.0 ns Write Cycle[23, 24] tWC Write cycle time 45.0 – ns tSCE CE1 LOW and CE2 HIGH to write end 35.0 – ns tAW Address setup to write end 35.0 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35.0 – ns tSD Data setup to write end 25.0 – ns tHD Data hold from write end 0 – ns – 18.0 ns 10.0 – ns tHZWE tLZWE WE LOW to High Z[19, 20, 21, 22] [19, 20, 21] WE HIGH to Low Z Notes 18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified otherwise. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. Tested initially and after any design or process changes that may affect these parameters. 21. These parameters are guaranteed by design and are not tested. 22. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 23. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 24. The minimum write cycle pulse width for Write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of tHZWE and tSD. Document Number: 002-29691 Rev. *A Page 9 of 19 CY62158G/CY62158GE MoBL Switching Waveforms Figure 6. Read Cycle No. 1 (Address Transition Controlled)[25, 26] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 7. Read Cycle No. 2 (OE Controlled)[26, 27, 28] ADDRESS tRC CE tPD t HZCE tACE OE t HZOE t DOE t LZOE DATA I /O HIGH IMPEDANCE DATAOUT VALID HIGH IMPEDANCE t LZCE VCC SUPPLY CURRENT tPU ISB Notes 25. The device is continuously selected. OE = VIL, CE = VIL. 26. WE is HIGH for read cycle. 27. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. Address valid prior to or coincident with CE LOW transition. Document Number: 002-29691 Rev. *A Page 10 of 19 CY62158G/CY62158GE MoBL Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled)[29, 30 31] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE OE tH Z O E D A T A I/O Note 31 tH D tS D D A T A IN V A L ID Notes 29. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 30. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH. 31. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 002-29691 Rev. *A Page 11 of 19 CY62158G/CY62158GE MoBL Switching Waveforms (continued) Figure 9. Write Cycle No. 2 (WE Controlled, OE Low)[32, 33, 34, 35] tWC ADDRESS tSCE CE tAW tSA tHA t PWE WE tSD t HZWE DATA I/O Note 35 t LZWE tHD DATAIN VALID Figure 10. Write Cycle No. 3 (CE Controlled)[32, 33, 34] tWC ADDRESS tSA tSCE CE tAW tHA t PWE WE OE t HZOE DATA I/O Note 35 tHD tSD DATAIN VALID Notes 32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. Data I/O is in high impedance state if CE = VIH, or OE = VIH. 34. The minimum write cycle pulse width should be equal to the sum of the tHZWE and tSD. 35. During this period I/O are in the output state. Do not apply input signals. Document Number: 002-29691 Rev. *A Page 12 of 19 CY62158G/CY62158GE MoBL Truth Table – CY62158G/CY62158GE CE1 CE2 WE OE I/Os Mode Power H X[36] X[36] X[36] High Z Deselect / Power Standby (ISB2) down X[36] L X[36] X[36] High Z Deselect / Power Standby (ISB2) down L H H L Data Out (I/O0–I/O7) Read L H H H High Z Output disabled Active (ICC) L H L X Data In (I/O0–I/O7) Write Active (ICC) Active (ICC) ERR Output – MoBL Output[37] Mode 0 Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. High-Z Device deselected / outputs disabled / Write operation Notes 36. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. 37. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 002-29691 Rev. *A Page 13 of 19 CY62158G/CY62158GE MoBL Ordering Information Speed (ns) Package Diagram Ordering Code CY62158G30-45ZSXI 45 51-85087 CY62158G30-45ZSXIT Package Type (all Pb-free) Operating Range 44-pin TSOP II (Pb-free) Industrial CY62158G30-45BVXI 51-85150 CY62158GE30-45BVXI 48-ball VFBGA Ordering Code Definitions CY 621 5 8 G XX - 45 ZS X I T X = blank or T blank = Bulk; T = Tape and Reel Temperature Grade: I = Industrial Pb-free Package Type: ZS = 44-pin TSOP II Speed Grade: 45 ns Voltage Range: XX = No character or 18 or 30 No character = 5 V typ; 30 = 3 V typ; 18 = 1.8 V typ Process Technology: G= 65 nm Bus Width: 8 = × 8 Density: 5 = 8-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 002-29691 Rev. *A Page 14 of 19 CY62158G/CY62158GE MoBL Package Diagrams Figure 11. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 002-29691 Rev. *A Page 15 of 19 CY62158G/CY62158GE MoBL Figure 12. 48-Ball VFBGA 6 × 8 × 1.0 mm BV48/BZ48/VCF048 Package Outline, 51-85150 51-85150 *I Document Number: 002-29691 Rev. *A Page 16 of 19 CY62158G/CY62158GE MoBL Acronyms Document Conventions Table 1. Acronyms Used in this Document Units of Measure Acronym Description Table 2. Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory µs microsecond VFBGA Very Fine-Pitch Ball Grid Array mA milliampere WE Write Enable mm millimeter ECC Error Correcting Code ns nanosecond Ω ohm % percent pF picofarad V volt Document Number: 002-29691 Rev. *A Symbol Unit of Measure Page 17 of 19 CY62158G/CY62158GE MoBL Document History Page Document Title: CY62158G/CY62158GE MoBL, 8-Mbit (1M × 8-bits) Static RAM with Error-Correcting Code (ECC) Document Number: 002-29691 Rev. ECN No. Submission Date *A 6814364 02/28/2020 Document Number: 002-29691 Rev. *A Description of Change Release to Web. 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