CY62167DV30L-55BVI

CY62167DV30 MoBL 16-Mbit (1M x 16) Static RAM Features • Very high speed: 55 ns • Wide voltage range: 2.20V – 3.60V • Ultra-low active power — Typical active current: 2 mA @ f = 1 MHz — Typical active current: 15 mA @ f = fmax • Ultra-low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered in a 48-ball BGA and 48-pin TSOPI reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. Functional Description[1] The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Logic Block Diagram A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA IN DRIVERS ROW DECODER 1M × 16 RAM Array SENSE AMPS I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER BHE WE OE BLE A11 A12 A13 A14 A15 A16 A17 A18 A19 CE2 CE1 Power-down Circuit BHE BLE CE2 CE1 Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05328 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 21, 2004 CY62167DV30 MoBL Pin Configuration[2, 3, 4, 5] FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 DNU A B C D E F G H I/O12 DNU I/O13 A19 A8 A14 A12 A9 48TSOPI (Forward) Top View A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Notes: 2. NC pins are not connected on the die. 3. DNU pins have to be left floating. 4. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 1M × 16 SRAM. The 48-TSOPI package can also be used as a 2M × 8 SRAM by tying the BYTE signal LOW. For 2M × 8 Functionality, please refer to the CY62168DV30 datasheet. In the 2M × 8 configuration, Pin 45 is A20. 5. Ball H6 for the FBGA package can be used to upgrade to a 32M density. Document #: 38-05328 Rev. *E Page 2 of 12 CY62167DV30 MoBL Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Supply Voltage to Ground Potential .......–0.2V to VCC + 0.3V DC Voltage Applied to Outputs in High-Z State[6, 7] .................................–0.2V to VCC + 0.3V DC Input Voltage[6, 7] .............................–0.2V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Device CY62167DV30L CY62167DV30LL Range Industrial Ambient Temperature –40°C to +85°C VCC[8] 2.20V to 3.60V Product Portfolio Power Dissipation Operating ICC(mA) VCC Range (V) Product CY62167DV30L CY62167DV30LL Min. 2.20 Typ.[9] 3.0 Max. 3.60 Speed (ns) 55 70 55 70 2 4 f = 1MHz Typ.[9] 2 Max. 4 f = fmax Typ.[9] 15 12 15 12 Max. 30 25 30 25 2.5 22 Standby ISB2(µA) Typ.[9] 2.5 Max. 30 Electrical Characteristics Over the Operating Range CY62167DV30-55 Parameter VOH VOL VIH Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Test Conditions IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1mA VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VIL IIX IOZ ICC ISB1 Input LOW Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC = VCCmax IOUT = 0 mA CMOS levels VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 –0.3 –0.3 –1 –1 15 2 2.5 2.5 2.5 2.5 Min. Typ. 2.0 2.4 0.4 0.4 VCC 1.8 +0.3V VCC 2.2 +0.3V 0.6 0.8 +1 +1 30 4 30 22 30 22 –0.3 –0.3 –1 –1 12 2 2.5 2.5 2.5 2.5 [9] CY62167DV30-70 2.0 2.4 0.4 0.4 VCC +0.3V VCC +0.3V 0.6 0.8 +1 +1 25 4 25 22 30 22 µA V V V V V V V V µA µA mA mA µA Max. Min. Typ.[9] Max. Unit VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz Automatic CE Power-down Current — CMOS Inputs Automatic CE Power-down Current — CMOS Inputs CE1 > VCC − 0.2V or CE2 < 0.2V L VIN > VCC – 0.2V, VIN < 0.2V) LL f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE, BLE), VCC = 3.60V CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V L LL ISB2 Notes: 6. VIL(min.) = –2.0V for pulse durations less than 20 ns. 7. VIH(Max) = VCC + 0.75V for pulse durations less than 20 ns. 8. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.)> = 500 µs. 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05328 Rev. *E Page 3 of 12 CY62167DV30 MoBL Capacitance[10, 11] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 8 10 Unit pF pF Thermal Resistance Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient)[10] Thermal Resistance (Junction to Case)[10] Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board BGA 55 16 TSOP I 60 4.3 Unit °C/W °C/W AC Test Loads and Waveforms VCC OUTPUT R1 VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns 50 pF INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V 3.0V 1103 1554 645 1.75 Unit Ω Ω Ω V Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[10] tR[12] Description VCC for Data Retention Data Retention Current L VCC= 1.5V CE1 > VCC – 0.2V, CE2 < 0.2V, LL VIN > VCC – 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 15 10 ns ns Typ.[9] Max. Unit V µA Chip Deselect to Data Retention Time Operation Recovery Time Data Retention Waveform[13] VCC CE1 or BHE.BLE VCC, min. tCDR DATA RETENTION MODE VDR > 1.5 V VCC, min. tR or CE2 Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. This applies for all packages. 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05328 Rev. *E Page 4 of 12 CY62167DV30 MoBL Switching Characteristics Over the Operating Range[14] 55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[17] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[15, 16] [15] 70 ns Max. Min. 70 55 70 10 55 25 70 35 5 20 25 10 20 25 0 55 55 70 70 10 20 25 70 60 60 0 0 45 60 30 0 20 25 10 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z [15] Min. 55 10 5 10 0 OE HIGH to High Z[15, 16] CE1 LOW and CE2 HIGH to Low Z[15] CE1 HIGH and CE2 LOW to High Z[15, 16] CE1 LOW and CE2 HIGH to Power-up CE1 HIGH and CE2 LOW to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[15] Z[15, 16] 55 40 40 0 0 40 40 25 0 10 10 BLE/BHE HIGH to HIGH WE HIGH to Low-Z Notes: 14. Test conditions for all parameters other than three-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 17. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. Document #: 38-05328 Rev. *E Page 5 of 12 CY62167DV30 MoBL Switching Waveforms Read Cycle 1 (Address Transition Controlled)[18, 19] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID Read Cycle 2 (OE Controlled)[19, 20] tAA DATA VALID ADDRESS tRC CE1 CE2 BHE/BLE tLZBE OE tLZOE HIGH IMPEDANCE tPU tLZCE 50% 50% tDOE DATA VALID tHZOE HIGH IMPEDANCE ICC ISB tDBE tHZBE tPD tACE tHZCE DATA OUT VCC SUPPLY CURRENT Notes: 18. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 19. WE is HIGH for read cycle. Document #: 38-05328 Rev. *E Page 6 of 12 CY62167DV30 MoBL Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[17, 21, 22, 23] tWC ADDRESS CE1 CE2 tAW tHA tSCE tSA WE tPWE BHE/BLE tBW OE tSD DATA I/O See Note 23 tHD VALID DATA tHZOE Notes: 20. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. 21. Data I/O is high-impedance if OE = VIH. 22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 23. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05328 Rev. *E Page 7 of 12 CY62167DV30 MoBL Switching Waveforms (continued) Write Cycle 2 (CE1 or CE2 Controlled)[17, 21, 22, 23] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE tBW BHE/BLE OE tSD DATA I/O See Note 23 tHD VALID DATA tHZOE Write Cycle 3 (WE Controlled, OE LOW)[22, 23] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tHA tSA WE tPWE tSD DATA I/O See Note 23 tHD tLZWE VALID DATA tHZWE Document #: 38-05328 Rev. *E Page 8 of 12 CY62167DV30 MoBL Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW)[22, 23] tWC ADDRESS CE1 CE2 tAW BHE/BLE tSA WE tBW tSCE tHA tPWE tSD tHD DATA I/O See Note 23 VALID DATA Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data Out (I/O8–I/O15) High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data In (I/O8–I/O15) Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05328 Rev. *E Page 9 of 12 CY62167DV30 MoBL Ordering Information Speed (ns) 55 55 70 70 Ordering Code CY62167DV30L-55BVI CY62167DV30LL-55BVI CY62167DV30L-55ZI CY62167DV30LL-55ZI CY62167DV30L-70BVI CY62167DV30LL-70BVI CY62167DV30L-70ZI CY62167DV30LL-70ZI Package Name Package Type BV48B 48-ball Fine Pitch BGA (8 mm × 9.5mm × 1 mm) Z48A BV48B Z48A 48 Pin TSOP I 48-ball Fine Pitch BGA (8 mm × 9.5mm × 1 mm) 48-pin TSOP I Operating Range Industrial Industrial Industrial Industrial Package Diagrams 48-Lead VFBGA (8 x 9.5 x 1 mm) BV48B TOP VIEW BOTTOM VIEW Ø0.05 M C A1 CORNER 1 2 3 4 5 6 Ø0.25 M C A B Ø0.30±0.05(48X) 6 5 4 3 2 1 A1 CORNER A B 9.50±0.10 0.75 C 9.50±0.10 5.25 D E F G H A B C D E 2.625 F G H A B 8.00±0.10 A 1.875 0.75 3.75 0.55 MAX. 0.25 C 0.21±0.05 B 0.10 C 0.15(4X) 8.00±0.10 SEATING PLANE 0.26 MAX. C 1.00 MAX 51-85178-** Document #: 38-05328 Rev. *E Page 10 of 12 CY62167DV30 MoBL Package Diagrams DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142 48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A MAX. 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE 0.002[0.05] 0.006[0.15] 0°-5° 51-85183-*A MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05328 Rev. *E Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62167DV30 MoBL Document History Page Document Title:CY62167DV30 MoBL 16-Mbit (1M x 16) Static RAM Document Number: 38-05328 REV. ** *A *B *C *D *E ECN NO. Issue Date 118408 123692 126555 127841 205701 238050 See ECN 09/30/02 02/11/03 04/25/03 09/10/03 Orig. of Change GUG DPM DPM XRJ AJU Description of Change New Data Sheet Changed Advanced to Preliminary Added package diagram Minor change: Changed Sunset Owner from DPM to HRT Added 48 TSOP I package Changed BYTE pin usage description for 48 TSOPI package KKV/AJU Replaced 48-lead VFBGA package diagram; Modified Package Name in Ordering Information table from BV48A to BV48B Document #: 38-05328 Rev. *E Page 12 of 12