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CY62167GN MoBL
16-Mbit (1M × 16/2M × 8) Static RAM
CY62167GN MoBL, 16-Mbit (1M × 16/2M × 8) Static RAM
Features
Functional Description
■
Ultra-low standby power
❐ Typical standby current: 5.5 µA
❐ Maximum standby current: 16 µA
■
TSOP I package configurable as 1M × 16 or 2M × 8 SRAM
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
■
Wide voltage range: 1.65 V to 2.2 V, and 4.5 V to 5.5 V
■
Easy memory expansion with CE1, CE2, and OE Features
■
Automatic power-down when deselected
■
CMOS for optimum speed and power
■
Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages
The CY62167GN is a high performance CMOS static RAM
organized as 1M words by 16 bits or 2M words by 8 bits. This
device features an advanced circuit design that provides an ultra
low active current. Ultra low active current is ideal for providing
More Battery Life (MoBL®) in portable applications such as
cellular telephones. The device also has an automatic power
down feature that reduces power consumption by 99 percent
when addresses are not toggling. Place the device into standby
mode when deselected (CE1 HIGH or CE2 LOW or both BHE and
BLE are HIGH). The input and output pins (I/O0 through I/O15)
are placed in a high impedance state when: the device is
deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH), or a write operation is in progress (CE1 LOW,
CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O8 through I/O15) is written into the location specified on
the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 13
for a complete description of read and write modes.
Logic Block Diagram
1M × 16/2M × 8
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power Down
Circuit
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE2
CE1
BHE
•
198 Champion Court
CE2
OE
CE1
BLE
BLE
Cypress Semiconductor Corporation
Document Number: 001-93628 Rev. *F
BYTE
BHE
WE
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 26, 2020
CY62167GN MoBL
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 13
Document Number: 001-93628 Rev. *F
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
CY62167GN MoBL
Pin Configuration
Figure 1. 48-ball VFBGA pinout (Top View) [1, 2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Figure 2. 48-pin TSOP I pinout (Top View) [2, 3]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V)
Min
CY62167GN18
Industrial
CY62167GN
Typ[4]
Speed
(ns)
Max
1.65
1.8
2.2
55
4.5
5.0
5.5
45
Operating ICC (mA)
f = 1 MHz
Typ[4]
Max
7
9
f = fmax
Typ[4]
Max
Standby ISB2
(µA)
Typ[4]
Max
29
32
7
26
29
36
5.5
16
Notes
1. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.
2. NC pins are not connected on the die.
3. The BYTE pin in the 48-pin TSOP I package has to be tied to VCC to use the device as a 1M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2M × 8
SRAM by tying the BYTE signal to VSS. In the 2M × 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-93628 Rev. *F
Page 3 of 20
CY62167GN MoBL
DC input voltage[5, 6] .................... –0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential[5, 6] ................ –0.3 V to VCC(max) + 0.3 V
DC voltage applied
to outputs in High Z state[5, 6] ...... –0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >200 mA
Operating Range
Device Range
Ambient
Temperature
VCC[7]
Industrial
–40 °C to +85 °C
1.65 V to 2.2 V,
4.5 V to 5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output HIGH voltage
Test Conditions
45 ns/ 55 ns
Min
Typ[8]
Max
1.65 < VCC < 2.2
IOH = –0.1 mA
1.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
–
–
–
0.2
VOL
Output LOW voltage
1.65 < VCC < 2.2
IOH = –0.1 mA VOH – 0.5[9]
IOL = 0.1 mA
–
4.5 < VCC < 5.5
IOL = 2.1 mA
–
–
0.4
VIH
Input HIGH voltage
1.65 < VCC < 2.2
1.4
–
VCC + 0.2
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
1.65 < VCC < 2.2
–0.2
–
0.4
Unit
V
V
V
VIL
Input LOW voltage
V
4.5 < VCC < 5.5
–0.5
–
0.8
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
µA
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = 22.22MHz (45 ns) VCC = VCC(max)
IOUT = 0 mA
f = 18.18MHz (55 ns) CMOS
levels
f = 1 MHz
–
29
36
mA
–
29
32
mA
–
7
9
mA
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 2V for pulse durations less than 20 ns.
7. Full Device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
8. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested
9. This parameter is guaranteed by design and not tested.
Document Number: 001-93628 Rev. *F
Page 4 of 20
CY62167GN MoBL
Electrical Characteristics (continued)
Over the Operating Range
Parameter
ISB1[10]
Description
Automatic power down
current – CMOS inputs
Test Conditions
CE1 > VCC – 0.2 V or CE2 < 0.2 V
45 ns/ 55 ns
Unit
Min
Typ[8]
Max
–
5.5
16
µA
–
5.5
6.5
µA
–
6.3
8.0
–
8.4
12.0
–
12.0
16.0
–
7.0
26.0
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
ISB2
[10]
Automatic Power-down
Current – CMOS Inputs
VCC = 4.5 V to 5.5 V
CE1 > VCC – 0.2 V or 25 °C[11]
CE2 < 0.2 V
40 °C[11]
or (BHE and BLE) > 70 °C[11]
VCC – 0.2 V,
85 °C
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, VCC = VCC(max)
Automatic Power-down
Current – CMOS Inputs
VCC = 1.65 V to 2.2 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
11. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
Document Number: 001-93628 Rev. *F
Page 5 of 20
CY62167GN MoBL
Capacitance
Parameter[12]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter[12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 48-pin TSOP I Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
31.50
57.99
°C/W
15.75
13.42
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
OUTPUT
R1
VHIGH
GND
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.80
1.20
1.75
1.77
V
VHIGH
1.8
2.5
3.0
5.0
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-93628 Rev. *F
Page 6 of 20
CY62167GN MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR[14, 15]
Data retention current
Conditions
VCC = 4.5 V to 5.5 V,
Min
Typ[13]
Max
Unit
1.0
–
–
V
–
5.5
16
µA
–
7.0
26.0
0
–
–
–
45/55
–
–
ns
CE1 > VCC 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
1.2 V < VCC < 2.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR[16]
Chip deselect to data retention
time
tR[17, 19]
Operation recovery time
Data Retention Waveform
VCC
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VDR > 1.0 V
tCDR
VCC(min)
tR
CE1 or
BHE.BLE
[18]
or
CE2
Notes
13. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
14. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
15. ICCDR is guaranteed only after the device is first powered up to VCC(min) and then brought down to VDR.
16. Tested initially and after any design or process changes that may affect these parameters.
17. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
18. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
19. These parameters are guaranteed by design and are not tested.
Document Number: 001-93628 Rev. *F
Page 7 of 20
CY62167GN MoBL
Switching Characteristics
Parameter[20]
45 ns
Description
55 ns
Unit
Min
Max
Min
Max
45.0
–
55.0
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
tOHA
Data hold from address change
tACE
tDOE
–
45.0
–
55.0
ns
10.0
–
10.0
–
ns
CE1 LOW and CE2 HIGH to data valid
–
45.0
–
55.0
ns
OE LOW to data valid
–
22.0
–
25.0
ns
5.0
–
5.0
–
ns
–
18.0
–
18.0
ns
10.0
–
10.0
–
ns
–
18.0
–
18.0
ns
[21, 22]
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z [21, 22, 23]
tLZCE
tHZCE
CE1 LOW and CE2 HIGH to Low Z
[21, 22]
CE1 HIGH and CE2 LOW to High Z
[21, 22, 23]
power-up[24]
tPU
CE1 LOW and CE2 HIGH to
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down[24]
–
45.0
–
55.0
ns
tDBE
BLE / BHE LOW to data valid
–
45.0
–
55.0
ns
5.0
–
5.0
–
ns
–
18.0
–
18.0
ns
tLZBE
tHZBE
BLE / BHE LOW to Low Z
[21, 22]
BLE / BHE HIGH to High Z
[21, 22, 23]
Write Cycle[25, 26]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
BLE / BHE LOW to write end
35
–
40
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to High Z
[21, 22, 23]
WE HIGH to Low Z
[21, 22]
Notes
20. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 3 on page 6.
21. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
22. Tested initially and after any design or process changes that may affect these parameters.
23. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
24. These parameters are guaranteed by design and are not tested.
25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write
26. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
Document Number: 001-93628 Rev. *F
Page 8 of 20
CY62167GN MoBL
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)[27, 28]
tRC
RC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[28, 29]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA I/O
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA OUT VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
27. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
28. WE is HIGH for read cycle.
29. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-93628 Rev. *F
Page 9 of 20
CY62167GN MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled)[30, 31, 32]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 33
DATA IN VALID
tHZOE
Notes
30. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
31. Data I/O is high impedance if OE = VIH.
32. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
33. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-93628 Rev. *F
Page 10 of 20
CY62167GN MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled)[34, 35]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 36
tHD
DATA IN VALID
tHZOE
Notes
34. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
35. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
36. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-93628 Rev. *F
Page 11 of 20
CY62167GN MoBL
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[37, 38]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 39
tHD
DATA IN VALID
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[37, 38]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 39
tHD
DATA IN VALID
Notes
37. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
38. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
39. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-93628 Rev. *F
Page 12 of 20
CY62167GN MoBL
Truth Table
CE1
H
CE2
[40]
X
X[40]
WE
X
OE
X
BHE
BLE
[40]
[40]
[40]
X
[40]
Power
High Z
Deselect/Power-down
Standby (ISB)
High Z
Deselect/Power-down
Standby (ISB)
Deselect/Power-down
Standby (ISB)
L
X
X
X
X
H
H
High Z
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
X
X
High Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
X
X
X
Mode
[40]
[40]
X
X
Inputs/Outputs
Note
40. The ‘X’ (Don’t care) state for the chip enables and Byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-93628 Rev. *F
Page 13 of 20
CY62167GN MoBL
Ordering Information
Speed Voltage Range
(ns)
55
1.65 V–2.2 V
Ordering Code
Package
Diagram
CY62167GN18-55BVXI
51-85150
48-ball VFBGA (6 × 8 × 1 mm),
Package Code: BV48
51-85183
48-pin TSOP I (Pb-free)
CY62167GN18-55BVXIT
45
4.5 V–5.5 V
CY62167GN-45ZXI
Package Type
Operating
Range
Industrial
CY62167GN-45ZXIT
Ordering Code Definitions
CY 621
6
7
G
N
XX - XX
XX X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = BV or Z
BV = 48-ball VFBGA; Z = 48-pin TSOP I
Speed Grade: XX = 55 ns or 45 ns
Voltage Range: XX = 18 or 30 or blank
18 = 1.8 V Typ; 30 = 3 V Typ; blank = 5 V Typ
N = No ECC feature
Process Technology: G = 65 nm
Bus Width: 7 = × 16
Density: 6 = 16-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-93628 Rev. *F
Page 14 of 20
CY62167GN MoBL
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 001-93628 Rev. *F
Page 15 of 20
CY62167GN MoBL
Package Diagrams (continued)
Figure 12. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-93628 Rev. *F
Page 16 of 20
CY62167GN MoBL
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
µA
microampere
I/O
Input/Output
µs
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
VFBGA
Very Fine-Pitch Ball Grid Array
ohm
WE
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-93628 Rev. *F
Symbol
Unit of Measure
Page 17 of 20
CY62167GN MoBL
Document History Page
Document Title: CY62167GN MoBL, 16-Mbit (1M × 16/2M × 8) Static RAM
Document Number: 001-93628
Rev.
ECN No.
Submission
Date
*B
5210733
07/04/2016
Changed status from Preliminary to Final.
*C
5420388
09/08/2016
Updated Electrical Characteristics:
Changed minimum value of VOH parameter corresponding to Test Condition
“2.7 < VCC < 3.6, IOH = –1.0 mA” from 2.2 V to 2.4 V.
Changed minimum value of VIH parameter corresponding to Test Condition
“2.2 < VCC < 2.7” from 2 V to 1.8 V.
Updated Note 5 (Replaced 2 ns with 20 ns).
Updated Note 6 (Replaced 2 ns with 20 ns).
Updated Ordering Information:
Updated part numbers (Added Tape and Reel parts).
Updated to new template.
Completing Sunset Review.
*D
5783985
06/23/2017
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter corresponding to Condition
“1.2 V < VCC < 2.2 V” from 5.5 A to 7.0 A.
Changed maximum value of ICCDR parameter corresponding to Condition
“1.2 V < VCC < 2.2 V” from 16.0 A to 26.0 A.
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
*E
6670237
09/20/2019
Updated Product Portfolio:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in “CY62167GN30”.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in “CY62167GN30”.
Updated Operating Range:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in “2.2 V to 3.6 V” in VCC column.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN19380.” and referred the same note in “2.2 V to 3.6 V” in VCC column.
Updated Electrical Characteristics:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in “VCC = 2.2 V to 3.6 V” in Description
column corresponding to ISB2 parameter.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN19380.” and referred the same note in ISB1 and ISB2 parameters.
Document Number: 001-93628 Rev. *F
Description of Change
Page 18 of 20
CY62167GN MoBL
Document History Page (continued)
Document Title: CY62167GN MoBL, 16-Mbit (1M × 16/2M × 8) Static RAM
Document Number: 001-93628
Rev.
ECN No.
Submission
Date
Description of Change
*E (cont.)
6670237
09/20/2019
Updated Data Retention Characteristics:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in ICCDR parameter.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN19380.” and referred the same note in ICCDR parameter.
*F
6817032
02/26/2020
Removed CY62167GN30 part related information in all instances across the document.
Removed 2.2 V to 3.6 V Voltage Range related information in all instances across the
document.
Updated Data Retention Characteristics:
Updated details in “Conditions” column corresponding to ICCDR parameter.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
Document Number: 001-93628 Rev. *F
Page 19 of 20
CY62167GN MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2014–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-93628 Rev. *F
Revised February 26, 2020
Page 20 of 20
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