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CY62167G/CY62167GE MoBL
16-Mbit (1M words × 16-bit/
2M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
CY62167G/CY62167GE MoBL, 16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Features
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
■
Ultra-low standby current
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 16 A
■
High speed: 45 ns/55 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction
■
Wide voltage range: 1.65 V to 2.2 V, and 4.5 V to 5.5 V
■
1.0-V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
48-pin TSOP I package configurable as 1M × 16 or 2M × 8
SRAM
■
Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY62167G and CY62167GE are high-performance CMOS,
low-power (MoBL®) SRAM devices with embedded ECC[1]. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62167GE device includes an
ERR pin that signals a single-bit error-detection and correction
event during a read cycle.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. You can
access read data on the I/O lines (I/O0 through I/O15). To perform
byte accesses, assert the required byte enable signal (BHE or
BLE) to read either the upper byte or the lower byte of data from
the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE1 HIGH / CE2 LOW for a dual chip enable device),
or the control signals are de-asserted (OE, BLE, BHE).
These devices have a unique Byte Power-down feature where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to the standby mode irrespective of
the state of the chip enables, thereby saving power.
On the CY62167GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
– CY62167G/CY62167GE on page 16 for a complete description
of read and write modes.
The CY62167G and CY62167GE devices are available in a
Pb-free 48-pin TSOP I package and 48-ball VFBGA packages.
The logic block diagrams are on page 2.
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
The device in the 48-pin TSOP I package can also be configured
to function as a 2M words × 8-bit device. Refer to the Pin
Configurations section for details.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
For a complete list of related documentation, click here.
Product Portfolio
Product
CY62167G(E)18
CY62167G(E)
Features and
Options (see the
Pin Configurations
section)
Single or Dual Chip
Enables
Optional ERR pin
Current Consumption
Range
Industrial
VCC Range
(V)
Speed
(ns)
Operating ICC, (mA)
f = fmax
Typ[2]
Max
Standby, ISB2 (µA)
Typ[2]
Max
1.65 V–2.2 V
55
29
32
7
26
4.5 V–5.5 V
45
29
36
5.5
16
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), and
VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-81537 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 7, 2020
CY62167G/CY62167GE MoBL
DATAIN DRIVERS
1M x 16 /
2M x 8
RAM ARRAY
ECC DECODE
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ECC ENCODE
SENSE AMPS
Logic Block Diagram – CY62167G
I/O0-I/O7
I/O8-I/O15
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
COLUMN DECODER
CE
BYTE
POWER DOWN
CIRCUIT
BHE
BHE
BLE
WE
CE2
OE
CE1
BLE
DATAIN DRIVERS
1M x 16 /
2M x 8
RAM ARRAY
ECC DECODE
ECC ENCODE
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
Logic Block Diagram – CY62167GE
ERR
I/O0-I/O7
I/O8-I/O15
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
COLUMN DECODER
CE
POWER DOWN
CIRCUIT
BYTE
BHE
BHE
BLE
WE
CE2
OE
CE1
BLE
Document Number: 001-81537 Rev. *R
Page 2 of 23
CY62167G/CY62167GE MoBL
Contents
Pin Configuration – CY62167G ........................................ 4
Pin Configuration – CY62167GE ..................................... 5
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
Data Retention Characteristics ..................................... 10
Data Retention Waveform .............................................. 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Truth Table – CY62167G/CY62167GE ........................... 16
ERR Output – CY62167GE ............................................. 16
Document Number: 001-81537 Rev. *R
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 3 of 23
CY62167G/CY62167GE MoBL
Pin Configuration – CY62167G
Figure 1. 48-ball VFBGA Pinout (Dual Chip Enable without ERR) – CY62167G [3]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Figure 2. 48-pin TSOP I Pinout (Dual Chip Enable without ERR) – CY62167G [3, 4]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Notes
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. Tie the BYTE pin in the 48-pin TSOP I package to VCC to use the device as a 1M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2M × 8 SRAM by
tying the BYTE signal to VSS. In the 2M × 8 configuration, pin 45 is the extra address line A20, while BHE, BLE, and I/O8 to I/O14 pins are not used and can be left floating.
Document Number: 001-81537 Rev. *R
Page 4 of 23
CY62167G/CY62167GE MoBL
Pin Configuration – CY62167GE
Figure 3. 48-ball VFBGA Pinout (Single Chip Enable with ERR) – CY62167GE [5, 6]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
ERR
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Figure 4. 48-ball VFBGA Pinout (Dual Chip Enable with ERR) – CY62167GE [5, 6]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
ERR
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Notes
5. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
6. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81537 Rev. *R
Page 5 of 23
CY62167G/CY62167GE MoBL
Pin Configuration – CY62167GE (continued)
Figure 5. 48-pin TSOP I Pinout (Dual Chip Enable with ERR) – CY62167GE [7, 8]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
ERR
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Notes
7. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
8. Tie the BYTE pin in the 48-pin TSOP I package to VCC to use the device as a 1M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2M × 8 SRAM by
tying the BYTE signal to VSS. In the 2M × 8 configuration, pin 45 is the extra address line A20, while the BHE, BLE, and I/O8 to I/O14 pins are not used and can be
left floating.
Document Number: 001-81537 Rev. *R
Page 6 of 23
CY62167G/CY62167GE MoBL
DC input voltage[9] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
to ground potential .............................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z state[9] .................................. –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC[10]
Industrial
–40 °C to +85 °C
1.65 V to 2.2 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
Description
Output
HIGH
voltage
Test Conditions
45/55 ns
Min
Typ [11]
Max
1.4
–
–
1.65 V to 2.2 V
VCC = Min, IOH = –0.1 mA
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VCC – 0.4[12]
–
–
–
–
0.2
VOL
Output LOW 1.65 V to 2.2 V
voltage
4.5 V to 5.5 V
VIH
Input HIGH
voltage[9]
1.65 V to 2.2 V
4.5 V to 5.5 V
VIL
Input LOW
voltage[9]
1.65 V to 2.2 V
4.5 V to 5.5 V
–
VCC = Min, IOL = 0.1 mA
VCC = Min, IOL = 2.1 mA
–
–
0.4
1.4
–
VCC + 0.2
–
2.2
–
VCC + 0.5
–
–0.2
–
0.4
–0.5
–
0.8
–
IIX
Input leakage current
GND < VIN < VCC
–1.0
–
+1.0
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
ICC
VCC operating supply current
VCC = Max, IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
–
29.0
36.0
f = 18.18 MHz
(55 ns)
–
29.0
32.0
f = 1 MHz
–
7.0
9.0
Unit
V
A
mA
Notes
9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
10. Full device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 200-µs wait time after VCC stabilizes to its operational value.
11. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
12. This parameter is guaranteed by design and is not tested.
Document Number: 001-81537 Rev. *R
Page 7 of 23
CY62167G/CY62167GE MoBL
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter
ISB1[13]
Description
Automatic Power-down
Current – CMOS Inputs;
VCC = 4.5 V to 5.5 V
Automatic Power-down
Current – CMOS Inputs
VCC = 1.65 V to 2.2 V
45/55 ns
Test Conditions
CE1 > VCC – 0.2 V or CE2 < 0.2 V
Min
Typ [11]
Max
–
5.5
16.0
–
7.0
26.0
Unit
A
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
ISB2[13]
Automatic Power-down
Current – CMOS Inputs
VCC = 4.5 V to 5.5 V
CE1 > VCC – 0.2V or
25 °C
–
5.5
6.5[14]
CE2 < 0.2 V or
40 °C
–
6.3
8.0[14]
70 °C
–
8.4
12.0[14]
85 °C
–
12.0
16.0
–
7.0
26.0
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, VCC = VCC(max)
Automatic Power-down
Current – CMOS Inputs
VCC = 1.65 V to 2.2 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
13. Chip enables (CE1 and CE2) and BYTE must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
14. The ISB2 maximum limits at 25 °C, 40 °C, and 70 °C are guaranteed by design and not 100% tested.
Document Number: 001-81537 Rev. *R
Page 8 of 23
CY62167G/CY62167GE MoBL
Capacitance
Parameter [15]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10.0
pF
10.0
pF
Thermal Resistance
Parameter [15]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 48-pin TSOP I Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
31.50
57.99
°C/W
15.75
13.42
°C/W
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms
VCC
OUTPUT
R1
VHIGH
GND
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.80
1.20
1.75
1.77
V
VHIGH
1.8
2.5
3.0
5.0
V
Note
15. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-81537 Rev. *R
Page 9 of 23
CY62167G/CY62167GE MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
VCC for data retention
–
ICCDR[17, 18]
Data retention current
1.2 V < VCC < 2.2 V,
Min
Typ [16]
Max
Unit
1.0
–
–
V
–
7.0
26.0
A
–
5.5
16.0
A
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
4.5 V < VCC < 5.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR[19]
Chip deselect to data retention
time
–
0.0
–
–
–
tR[19, 20]
Operation recovery time
–
45/55
–
–
ns
Data Retention Waveform
Figure 7. Data Retention Waveform [21]
VCC
VCC (min)
tCDR
DATA RETENTION MODE
VDR = 1.0 V
VCC (min)
tR
CE1 or
BHE. BLE
CE2
Notes
16. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
17. Chip enables (CE1 and CE2) and BYTE must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
18. ICCDR is guaranteed only after the device is first powered up to VCC(min) and then brought down to VDR.
19. These parameters are guaranteed by design and are not tested.
20. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
21. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-81537 Rev. *R
Page 10 of 23
CY62167G/CY62167GE MoBL
Switching Characteristics
Parameter [22]
45 ns
Description
55 ns
Unit
Min
Max
Min
Max
45.0
–
55.0
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid/Address to ERR valid
–
45.0
–
55.0
ns
tOHA
Data hold from address change/ERR hold from address
change
10.0
–
10.0
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
valid
–
45.0
–
55.0
ns
tDOE
OE LOW to data valid/OE LOW to ERR valid
–
22.0
–
25.0
ns
5.0
–
5.0
–
ns
–
18.0
–
18.0
ns
10.0
–
10.0
–
ns
–
18.0
–
18.0
ns
Z[23, 24]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[23, 24, 25]
tLZCE
tHZCE
CE1 LOW and CE2 HIGH to Low
Z[23, 24]
CE1 HIGH and CE2 LOW to High
Z[23, 24, 25]
power-up[26]
tPU
CE1 LOW and CE2 HIGH to
0.0
–
0.0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down[26]
–
45.0
–
55.0
ns
tDBE
BLE/BHE LOW to data valid
–
45.0
–
55.0
ns
5.0
–
5.0
–
ns
–
18.0
–
18.0
ns
tLZBE
tHZBE
BLE/BHE LOW to Low
Z[23]
BLE/BHE HIGH to High
Z[23, 25]
Write Cycle [27, 28]
tWC
Write cycle time
45.0
–
55.0
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35.0
–
40.0
–
ns
tAW
Address setup to write end
35.0
–
40.0
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35.0
–
40.0
–
ns
tBW
BLE/BHE LOW to write end
35.0
–
40.0
–
ns
tSD
Data setup to write end
25.0
–
25.0
–
ns
tHD
Data hold from write end
0.0
–
0.0
–
ns
–
18.0
–
20.0
ns
10.0
–
10.0
–
ns
tHZWE
tLZWE
WE LOW to High
Z[23, 24, 25]
WE HIGH to Low
Z[23, 24]
Notes
22. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in Figure 6 on page 9, unless specified otherwise.
23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
24. Tested initially and after any design or process changes that may affect these parameters.
25. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
26. These parameters are guaranteed by design and are not tested.
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
28. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
Document Number: 001-81537 Rev. *R
Page 11 of 23
CY62167G/CY62167GE MoBL
Switching Waveforms
Figure 8. Read Cycle No. 1 of CY62167G (Address Transition Controlled) [29, 30]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 9. Read Cycle No. 1 of CY62167GE (Address Transition Controlled) [29, 30]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
29. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE, or both = VIL.
30. WE is HIGH for read cycle.
Document Number: 001-81537 Rev. *R
Page 12 of 23
CY62167G/CY62167GE MoBL
Switching Waveforms (continued)
Figure 10. Read Cycle No. 2 (OE Controlled) [31, 32, 33, 34]
ADDRESS
tR C
CE
tP D
tH Z C E
tA C E
OE
tH Z O E
tD O E
tL Z O E
BHE/
BLE
tD B E
tL Z B E
D A T A I/O
tH Z B E
H IG H IM P E D A N C E
H IG H
IM P E D A N C E
D A T A O U T V A L ID
tLZC E
tP U
V CC
SUPPLY
CURRENT
IS B
Figure 11. Write Cycle No. 1 (WE Controlled, OE LOW) [32, 34, 35, 36]
tW C
ADDRESS
tS C E
CE
tB W
BHE/
BLE
tS A
tA W
tH A
tP W E
WE
tH Z W E
D A T A I/O
Note 37
tS D
tLZW E
tH D
D A T A IN V A L ID
Notes
31. WE is HIGH for read cycle.
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. Address valid prior to or coincident with CE LOW transition.
34. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
35. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
36. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
37. During this period, the I/Os are in the output state. Do not apply input signals.
Document Number: 001-81537 Rev. *R
Page 13 of 23
CY62167G/CY62167GE MoBL
Switching Waveforms (continued)
Figure 12. Write Cycle No. 2 (CE Controlled) [38, 39, 40]
tWC
ADDRESS
tSA
t SCE
CE
tAW
tHA
t PWE
WE
tBW
BHE/
BLE
OE
t HZOE
DATA I/ O
Note 41
tHD
tSD
DATAIN VALID
Notes
38. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
39. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
40. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
41. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-81537 Rev. *R
Page 14 of 23
CY62167G/CY62167GE MoBL
Switching Waveforms (continued)
Figure 13. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [42, 43, 44]
tW C
ADDRESS
tS C E
CE
t AW
tS A
tH A
t BW
BHE/
B LE
tP W E
WE
t H ZW E
D A TA I/O
tH D
tS D
Note 45
t LZW E
D A TA IN V A LID
Figure 14. Write Cycle No. 5 (WE Controlled) [42, 43, 44]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
tB W
B H E /B L E
OE
tH Z O E
D A T A I/O
Note 45
tH D
tS D
D A T A IN V A L I D
Notes
42. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
43. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
44. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
45. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-81537 Rev. *R
Page 15 of 23
CY62167G/CY62167GE MoBL
Truth Table – CY62167G/CY62167GE
BYTE [46] CE1
WE
OE
BHE
BLE
[47]
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB) 2M × 8/1M × 16
X
L
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB) 2M × 8/1M × 16
X
X[47]
[47]
X
X
H
H
High-Z
Deselect/Power-down Standby (ISB)
H
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
1M × 16
H
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15)
Read
Active (ICC)
1M × 16
H
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
1M × 16
H
L
H
H
H
L
H
High-Z
Output disabled
Active (ICC)
1M × 16
H
L
H
H
H
H
L
High-Z
Output disabled
Active (ICC)
1M × 16
H
L
H
H
H
L
L
High-Z
Output disabled
Active (ICC)
1M × 16
H
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
1M × 16
H
L
H
L
X
H
L
Data In (I/O0–I/O7);
High-Z (I/O8–I/O15)
Write
Active (ICC)
1M × 16
H
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
1M × 16
L
L
H
H
L
X
X
Data Out (I/O0–I/O7)
Read
Active (ICC)
2M × 8
L
L
H
H
H
X
X
High-Z
Output disabled
Active (ICC)
2M × 8
L
L
H
L
X
X
X
Data In (I/O0–I/O7)
Write
Active (ICC)
2M × 8
[47]
H
X
[47]
X
CE2
X
X
Inputs/Outputs
Mode
Power
Configuration
1M × 16
ERR Output – CY62167GE
Output[48]
Mode
0
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
High-Z
Device deselected / outputs disabled / Write operation
Notes
46. This pin is available only in the 48-pin TSOP I package. Tie the BYTE to VCC to configure the device in the 1M × 16 option. The 48-pin TSOP I package can also be
used as a 2M × 8 SRAM by tying the BYTE signal to VSS.
47. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
48. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81537 Rev. *R
Page 16 of 23
CY62167G/CY62167GE MoBL
Ordering Information
Speed
(ns)
45
Voltage
Range
Ordering Code
4.5 V–5.5 V CY62167G-45BVXI
Package
Diagram
Package Type
(all Pb-free)
Key Features /
Differentiators
ERR Pin /
Ball
51-85150 48-ball VFBGA
Dual Chip Enable No
51-85183 48-pin TSOP I
Dual Chip Enable No
Operating
Range
Industrial
CY62167G-45BVXIT
CY62167G-45ZXI
CY62167G-45ZXIT
CY62167GE-45ZXI
Yes
CY62167GE-45ZXIT
55
1.65 V–2.2 V CY62167GE18-55BVXI
51-85150 48-ball VFBGA
Dual Chip Enable Yes
CY62167GE18-55BVXIT
CY62167G18-55BVXI
No
CY62167G18-55BVXIT
CY62167G18-55ZXI
51-85183 48-pin TSOP I
No
CY62167G18-55ZXIT
Ordering Code Definitions
CY 621
6
7
G
E
XX - XX XX X X X X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: X = I
I = Industrial
Pb-free
X = blank or 1
blank = Dual Chip Enable; 1 = Single Chip Enable
Package Type: XX = BV or Z
BV = 48-ball VFBGA; Z = 48-pin TSOP I
Speed Grade: XX = 45 or 55
45 = 45 ns; 55 = 55ns
Voltage Range: XX = blank or 18
blank = 5 V typ; 18 = 1.8 V typ
ERR output: Single-bit error correction indicator
Process Technology: G = 65 nm
Bus Width: 7 = × 16
Density: 6 = 16-Mbit
Family Code: 621 = MoBL® SRAM family
Company ID: CY = Cypress
Document Number: 001-81537 Rev. *R
Page 17 of 23
CY62167G/CY62167GE MoBL
Package Diagrams
Figure 15. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 001-81537 Rev. *R
Page 18 of 23
CY62167G/CY62167GE MoBL
Package Diagrams (continued)
Figure 16. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-81537 Rev. *R
Page 19 of 23
CY62167G/CY62167GE MoBL
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary metal oxide semiconductor
A
microampere
I/O
Input/output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static random access memory
mm
millimeter
TSOP
Thin small outline package
ns
nanosecond
VFBGA
Very fine-pitch ball grid array
ohm
WE
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-81537 Rev. *R
Symbol
Unit of Measure
Page 20 of 23
CY62167G/CY62167GE MoBL
Document History Page
Document Title: CY62167G/CY62167GE MoBL, 16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with
Error-Correcting Code (ECC)
Document Number: 001-81537
Rev.
ECN No.
Submission
Date
*M
4791835
06/15/2015
Changed status from Preliminary to Final.
Completing Sunset Review.
*N
5027105
11/25/2015
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding to Operating
Range “2.7 V to 3.6 V” and Test Condition “VCC = Min, IOH = –1.0 mA”.
*O
5439177
09/16/2016
Updated DC Electrical Characteristics:
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding to Operating
Range “2.2 V to 2.7 V”.
Updated Note 9 (Replaced 2 ns with 20 ns).
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
*P
5751153
05/26/2017
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Completing Sunset Review.
*Q
6607623
09/23/2019
Updated Product Portfolio:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in CY62167G(E)30.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in CY62167G(E)30.
Updated DC Electrical Characteristics:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in “2.2 V to 2.7 V”, “2.7 V to 3.6 V” in
“Description” column corresponding to VOH, VOL, VIH, VIL parameters.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in “2.2 V to 2.7 V”, “2.7 V to 3.6 V” in “Description”
column corresponding to VOH, VOL, VIH, VIL parameters.
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in “VCC = 2.2 V to 3.6 V” in “Description”
column corresponding to ISB1, ISB2 parameters.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in “VCC = 2.2 V to 3.6 V” in “Description” column
corresponding to ISB1, ISB2 parameters.
Document Number: 001-81537 Rev. *R
Description of Change
Page 21 of 23
CY62167G/CY62167GE MoBL
Document History Page (continued)
Document Title: CY62167G/CY62167GE MoBL, 16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with
Error-Correcting Code (ECC)
Document Number: 001-81537
Rev.
ECN No.
Submission
Date
Description of Change
*Q (cont.)
6607623
09/23/2019
Updated Data Retention Characteristics:
Added Note “The 3V Typical VCC device is offered with improved ICC, ISB1 and ISB2
specifications compared to the current revision with same marketing part number. The new
device will be in production from WW1952. For more information, please contact Cypress
Sales representative.” and referred the same note in “2.2 V < VCC < 3.6 V” in “Conditions”
column corresponding to ICCDR parameter.
Added Note “For next version of this 3V Typical VCC device, kindly refer here. Further details
about improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in “2.2 V < VCC < 3.6 V” in “Conditions” column
corresponding to ICCDR parameter.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
Completing Sunset Review.
*R
6801217
02/07/2020
Removed “2.2 V to 3.6 V” voltage range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Document Number: 001-81537 Rev. *R
Page 22 of 23
CY62167G/CY62167GE MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/iot
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Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
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cypress.com/usb
cypress.com/wireless
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and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-81537 Rev. *R
Revised February 7, 2020
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