CY62167EV30 Automotive MoBL®
16-Mbit (1M × 16/2M × 8) Static RAM
16-Mbit (1M × 16/2M × 8) Static RAM
Features
■
TSOP I package configurable as 1M × 16 or 2M × 8 SRAM
■
Very high speed: 45 ns
■
Temperature ranges
❐ Automotive-A: –40 °C to +85 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Ultra-low standby power
❐ Typical standby current: 1.5 A
❐ Maximum standby current: 12 A
■
Ultra-low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
■
Automatic power-down when deselected
■
CMOS for optimum speed and power
■
Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages
Functional Description
The CY62167EV30 is a high-performance CMOS static RAM
organized as 1M words by 16 bits or 2M words by 8 bits. This
device features an advanced circuit design that provides an ultra
low active current. Ultra low active current is ideal for providing
More Battery Life (MoBL®) in portable applications such as
cellular telephones. The device also has an automatic power
down feature that reduces power consumption by 99 percent
when addresses are not toggling. Place the device in standby
mode when deselected (CE1 HIGH or CE2 LOW or both BHE and
BLE are HIGH). The input and output pins (I/O0 through I/O15)
are placed in a high-impedance state when: the device is
deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH), or a write operation is in progress (CE1 LOW,
CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O8 through I/O15) is written into the location specified on
the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
1M × 16 / 2M x 8
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power Down
Circuit
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE2
CE1
BHE
•
198 Champion Court
CE2
OE
CE1
BLE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05446 Rev. *Q
BYTE
BHE
WE
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 2, 2018
CY62167EV30 Automotive MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 12
Document Number: 38-05446 Rev. *Q
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY62167EV30 Automotive MoBL®
Pin Configuration
Figure 1. 48-ball VFBGA Pinout (Top View) [1, 2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Figure 2. 48-pin TSOP I Pinout (Top View) [2, 3]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
CY62167EV30LL
Range
Automotive-A
VCC Range (V)
Min
Typ[4]
Max
2.2
3.0
3.6
Speed
(ns)
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2
(A)
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
2.2
4.0
25
30
1.5
12
Notes
1. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.
2. NC pins are not connected on the die.
3. The BYTE pin in the 48-pin TSOP I package has to be tied to VCC to use the device as a 1 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8
SRAM by tying the BYTE signal to VSS. In the 2 M × 8 configuration, Pin 45 is A20, while BHE, BLE, and I/O8 to I/O14 pins are not used.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05446 Rev. *Q
Page 3 of 19
CY62167EV30 Automotive MoBL®
DC input voltage [5, 6] ....... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential [5, 6] .... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
DC voltage applied to outputs
in High Z state [5, 6] ........... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >200 mA
Operating Range
Ambient
Temperature
CY62167EV30LL Automotive-A –40 °C to +85 °C
Device
VCC [7]
Range
2.2 V to
3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Automotive-A)
Min Typ [8]
VOH
Output HIGH voltage
VOL
Output LOW voltage
VIH
Input HIGH voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
VIL
Input LOW voltage
2.2 < VCC < 2.7
For VFBGA package –0.3
For TSOP I package –0.3
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
2.2 < VCC < 2.7
IOL = 0.1 mA
–
2.7 < VCC < 3.6
IOL = 2.1 mA
2.7 < VCC < 3.6
Max
Unit
–
V
–
–
V
–
0.4
V
–
–
0.4
V
1.8
–
VCC + 0.3
V
2.2
–
VCC + 0.3
V
–0.3
–
0.6
V
–
0.8
V
–
0.7[9]
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
ISB1[10]
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
–
25
30
mA
–
2.2
4.0
mA
–
1.5
12
A
VCC = VCC(max)
Temperature = 25 °C
–
1.5
3.0[11]
A
VCC = 3.0 V,
(BHE and BLE) > VCC – 0.2 V, Temperature
= 40 °C
VIN > VCC – 0.2 V or
VCC = VCC(max)
VIN < 0.2 V, f = 0
Temperature = 85 °C
–
–
3.5[11]
–
–
12
f = 1 MHz
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V
CMOS inputs
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
ISB2
[10]
Automatic power down current – CE1 > VCC – 0.2 V or
CMOS inputs
CE2 < 0.2 V or
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation assumes a 100-s ramp time from 0 to VCC(min) and 200-s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V. This is
applicable to the TSOP I package only.
10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB1/ISB2 / ICCDR spec. Other inputs can be left floating
11. This parameter is guaranteed by design.
Document Number: 38-05446 Rev. *Q
Page 4 of 19
CY62167EV30 Automotive MoBL®
Capacitance
Parameter [12]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 48-pin TSOP I Unit
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
55
60
°C/W
16
4.3
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
GND
30 pF
R2
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.2 V to 2.7 V
2.7 V to 3.6 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05446 Rev. *Q
Page 5 of 19
CY62167EV30 Automotive MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Min Typ [13] Max Unit
Conditions
VDR
VCC for data retention
ICCDR[14]
Data retention current VCC = 1.5 V to 3.0 V,
Automotive-A
All packages
1.5
–
–
V
–
–
10
A
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR[15]
Chip deselect to data
retention time
0
–
–
–
tR[16]
Operation recovery
time
45
–
–
ns
Data Retention Waveform
VCC
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VDR > 1.5 V
tCDR
VCC(min)
tR
CE1 or
BHE.BLE
[17]
or
CE2
Notes
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
14. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
17. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05446 Rev. *Q
Page 6 of 19
CY62167EV30 Automotive MoBL®
Switching Characteristics
Parameter [18, 19]
Description
45 ns (Automotive-A)
Unit
Min
Max
45
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[20]
5
–
ns
–
18
ns
10
–
ns
–
18
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z [20, 21]
CE1 LOW and CE2 HIGH to Low Z
[20]
tHZCE
CE1 HIGH and CE2 LOW to High Z
[20, 21]
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
45
ns
tDBE
BLE / BHE LOW to data valid
–
45
ns
10
–
ns
–
18
ns
tLZCE
tLZBE
tHZBE
BLE / BHE LOW to Low Z
[20]
BLE / BHE HIGH to High Z
[20, 21]
Write Cycle [22, 23]
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE / BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
tHZWE
tLZWE
WE LOW to High Z
[20, 21]
WE HIGH to Low Z
[20]
Notes
18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 3 on page 5.
19. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the application notes AN13842 and AN66311. However, the issue has been fixed and is in production now, and hence, these application notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
20. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
21. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
22. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
23. The minimum pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05446 Rev. *Q
Page 7 of 19
CY62167EV30 Automotive MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [24, 25]
tRC
RC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [25, 26]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA I/O
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA OUT VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
24. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
25. WE is HIGH for read cycle.
26. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 38-05446 Rev. *Q
Page 8 of 19
CY62167EV30 Automotive MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [27, 28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 30
DATA IN VALID
tHZOE
Notes
27. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
28. Data I/O is high impedance if OE = VIH.
29. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
30. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 38-05446 Rev. *Q
Page 9 of 19
CY62167EV30 Automotive MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled) [31, 32]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 33
tHD
DATA IN VALID
tHZOE
Notes
31. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
32. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
33. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 38-05446 Rev. *Q
Page 10 of 19
CY62167EV30 Automotive MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW) [34]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 35
tHD
DATA IN VALID
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW) [34]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 35
tHD
DATA IN VALID
Notes
34. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
35. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 38-05446 Rev. *Q
Page 11 of 19
CY62167EV30 Automotive MoBL®
Truth Table
CE1
CE2
H
X[36]
WE
X
OE
X
BHE
BLE
[36]
[36]
[36]
X
X
Mode
Power
High Z
Deselect/Power-down
Standby (ISB)
High Z
Deselect/Power-down
Standby (ISB)
Deselect/Power-down
Standby (ISB)
[36]
L
X
X
[36]
[36]
X
X
H
H
High Z
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
X
X
X
[36]
Inputs/Outputs
X
X
Note
36. The ‘X’ (Don’t care) state for the chip enables and Byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 38-05446 Rev. *Q
Page 12 of 19
CY62167EV30 Automotive MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62167EV30LL-45BVXA
51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free),
Package Code: BZ48
CY62167EV30LL-45ZXA
51-85183 48-pin TSOP I (Pb-free)
Operating
Range
Automotive-A
Ordering Code Definitions
CY 621 6
7
E V30 LL - 45
XX X
X
Temperature Grade: X = A
A = Automotive-A
Pb-free
Package Type: XX = BV or Z
BV = 48-ball VFBGA
Z = 48-pin TSOP I
Speed Grade: 45 ns
LL = Low Power
Voltage Range: V30 = 3 V typical
Process Technology: E = Low Power
Bus Width = × 16
Density = 16-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05446 Rev. *Q
Page 13 of 19
CY62167EV30 Automotive MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *H
Document Number: 38-05446 Rev. *Q
Page 14 of 19
CY62167EV30 Automotive MoBL®
Package Diagrams (continued)
Figure 12. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 38-05446 Rev. *Q
Page 15 of 19
CY62167EV30 Automotive MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
A
microampere
I/O
input/output
s
microsecond
OE
output enable
mA
milliampere
SRAM
static random access memory
mm
millimeter
TSOP
thin small outline package
ns
nanosecond
VFBGA
very fine-pitch ball grid array
ohm
WE
write enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-05446 Rev. *Q
Symbol
Unit of Measure
Page 16 of 19
CY62167EV30 Automotive MoBL®
Document History Page
Document Title: CY62167EV30 Automotive MoBL®, 16-Mbit (1M × 16/2M × 8) Static RAM
Document Number: 38-05446
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
202600
AJU
01/23/2004
*A
463674
NXR
See ECN
Description of Change
New data sheet.
Changed status from Advance Information to Preliminary
Removed ‘L’ bin and 35 ns speed bin from product offering
Modified Data sheet to include x8 configurability.
Changed ball E3 in FBGA pinout from DNU to NC
Changed the ISB2(Typ) value from 1.3 Ato1.5 A
Changed the ICC(Max) value from 40 mA to 25 mA
Changed Vcc stabilization time in footnote #9 from 100 µs to 200 µs
Changed the AC Test Load Capacitance value from 50 pF to 30 pF
Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns
Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns
Changed tLZOE from 3 ns to 5 ns.
Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns
Changed tSCE, tAW, and tBW from 40 ns to 35 ns
Changed tPE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Updated 48-ball FBGA Package Information.
Updated the Ordering Information table
*B
469169
NSI
See ECN
Minor Change: Moved to external web
*C
1130323
VKN
See ECN
Changed status from Preliminary to Final.
Changed ICC max spec from 2.8 mA to 4.0 mA for f = 1MHz
Changed ICC typ spec from 22 mA to 25 mA for f = fmax
Changed ICC max spec from 25 mA to 30 mA for f = fmax
Added VIL spec for TSOP I package and footnote# 9
Added footnote# 10 related to ISB2 and ICCDR
Changed ISB1 and ISB2 spec from 8.5 A to 12 A
Changed ICCDR spec from 8 A to 10 A
Added footnote# 15 related to AC timing parameters
*D
1323984
VKN /
AESA
See ECN
Modified ICCDR spec for TSOP I package
Added 48-ball VFBGA (6 × 7 × 1mm) package
Added footnote# 1 related to VFBGA (6 × 7 × 1mm) package
Updated Ordering Information table
*E
2678799
VKN /
PYRS
03/25/2009
Added Automotive-A information
*F
2720234
VKN /
AESA
06/17/2009
Included -45BVXA part in the Ordering information table
*G
2880574
VKN
02/18/2010
Modified ICCDR spec from 8 A to 10 A for Auto-A grade.
Added Contents.
Updated all package diagrams.
Updated links in Sales, Solutions, and Legal Information.
*H
2934396
VKN
06/03/10
*I
3006301
RAME
08/12/2010
Document Number: 38-05446 Rev. *Q
Added footnote #25 related to chip enable.
Updated template.
Included BHE and BLE in ISB1, ISB2, and ICCDR test conditions to reflect Byte
power down feature.
Removed 48-ball VFBGA (6 × 7 × 1 mm) package related information.
Added Acronyms and Ordering code definition.
Format updates to match template.
Page 17 of 19
CY62167EV30 Automotive MoBL®
Document History Page (continued)
Document Title: CY62167EV30 Automotive MoBL®, 16-Mbit (1M × 16/2M × 8) Static RAM
Document Number: 38-05446
Rev.
ECN No.
Orig. of
Change
Submission
Date
*J
3295175
RAME
06/29/2011
Updated Package Diagrams.
Added Document Conventions.
Removed reference to AN1064 SRAM system guidelines.
Added ISB1 to footnotes 10 and 14. Added byte enables to footnote 36 and
referenced to Truth table.
*K
3411301
TAVA
10/17/2011
Updated Switching Waveforms.
Updated Package Diagrams.
Updated to new template.
*L
3667939
TAVA
07/09/2012
Updated Ordering Information (No change in part numbers, updated details in
Package Type column only).
Updated Package Diagrams (Spec 51-85150 (Updated figure caption only, no
change in revision)).
*M
4102969
VINI
08/23/2013
Updated Switching Characteristics:
Updated Note 19.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
Updated to new template.
Completing Sunset Review.
*N
4574264
VINI
11/19/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 5 and 6 in “Supply voltage to ground potential”.
Updated Switching Characteristics:
Added Note 23 and referred the same note in “Write Cycle”.
*O
4715413
VINI
04/07/2015
Updated Electrical Characteristics:
Updated details in “Test Conditions” column corresponding to ISB2 parameter
and added corresponding values.
Added Note 11 and referred the same note in maximum values of ISB2
parameter corresponding to Test Conditions “VCC = VCC(max),
Temperature = 25 °C” and “VCC = 3.0 V, Temperature = 40 °C”.
*P
5734005
VINI
05/11/2017
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
*Q
6269846
NILE
08/02/2018
Removed references to industrial device from this datasheet.
Refer to spec 002-24706 for details about Industrial option.
Document Number: 38-05446 Rev. *Q
Description of Change
Page 18 of 19
CY62167EV30 Automotive MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/arm
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Internet of Things
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cypress.com/interface
cypress.com/iot
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Microcontrollers
cypress.com/mcu
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cypress.com/psoc
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Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications.To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners..
Document Number: 38-05446 Rev. *Q
Revised August 2, 2018
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
Page 19 of 19
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