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CY62168G/CY62168GE MoBL
16-Mbit (2M words × 8 bits) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC)
Features
Devices with a single chip enable input are accessed by
asserting the chip enable input (CE) LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
■
Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 16 A
■
High speed: 45 ns/55 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction
■
Wide voltage range: 1.65 V to 2.2 V, 4.5 V to 5.5 V
■
1.0 V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
ERR pin to indicate 1-bit error detection and correction
■
Available in Pb-free 48-ball VFBGA package
Functional Description
CY62168G and CY62168GE are high-performance CMOS
low-power (MoBL®) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62168GE device includes an
error indication pin that signals a single-bit error-detection and
correction event during a read cycle.
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written
into the location specified on the address pins (A0 through A20).
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62168G/CY62168GE on page
14 for a complete description of read and write modes.
On CY62168GE devices, the detection and correction of a single
bit error in the accessed location is indicated by the assertion of
the ERR output (ERR = HIGH) [1].
The CY62168G and CY62168GE devices are available in a
Pb-free 48-pin VFBGA package. The logic block diagrams are
on page 2.
For a complete list of related resources, click here.
Product Portfolio
Power Dissipation
Product
CY62168G(E)18
CY62168G(E)
Features and Options
(see Pin
Configurations
section)
Single or dual Chip
Enables
Range
Industrial
VCC Range
(V)
Speed Operating ICC, (mA) Standby, I
SB2 (µA)
(ns)
f = fmax
Typ[2]
Max
Typ[2]
Max
1.65 V–2.2 V
55
29
32
7
26
4.5 V–5.5 V
45
29
36
5.5
16
Optional ERR pin
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-84771 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 26, 2020
CY62168G/CY62168GE MoBL
Logic Block Diagram – CY62168G
2M x 8
RAM ARRAY
SENSE
AMPLIFIERS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ECC DECODER
DATAIN
DRIVERS
ECC ENCODER
I/O0‐I/O7
COLUMN
DECODER
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
WE
OE
CE2
CE1
Logic Block Diagram – CY62168GE
2M x 8
RAM ARRAY
SENSE
AMPLIFIERS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O0‐I/O7
ERR
WE
OE
CE2
CE1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
COLUMN
DECODER
ECC DECODER
DATAIN
DRIVERS
ECC ENCODER
Document Number: 001-84771 Rev. *K
Page 2 of 20
CY62168G/CY62168GE MoBL
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 10
Truth Table – CY62168G/CY62168GE ........................... 14
ERR Output – CY62168GE ............................................. 14
Document Number: 001-84771 Rev. *K
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 3 of 20
CY62168G/CY62168GE MoBL
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) pinout[3]
CY62168G
1
2
3
4
5
6
NC
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
A18
A16
I/O6
VSS
E
I/O3
NC
A14
A15
NC
I/O7
F
NC
NC
A12
A13
WE
NC
G
A19
A8
A9
A10
A11
A20
H
Figure 2. 48-ball VFBGA (6 × 8 × 1 mm) pinout[3, 4]
CY62168GE
Note
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-84771 Rev. *K
Page 4 of 20
CY62168G/CY62168GE MoBL
DC input voltage[5] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Supply voltage to ground potential ...................–0.5 V to 6 V
DC voltage applied to outputs
in High Z state[5] .................................. –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC[6]
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
Description
Output HIGH
voltage
VIH
VIL
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage[9]
45 ns/55 ns
Unit
Min
Typ [7]
Max
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
1.4
–
–
V
VCC = Min, IOH = –1.0 mA
2.4
–
–
V
–
–
V
4.5 V to 5.5 V
4.5 V to 5.5 V
VOL
Test Conditions
VCC = Min, IOH = –0.1 mA
VCC – 0.4
[8]
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
–
0.2
V
VCC = Min, IOL = 2.1 mA
–
–
0.4
V
1.65 V to 2.2 V –
1.4
–
VCC + 0.2
V
4.5 V to 5.5 V
2.2
–
VCC + 0.5
V
4.5 V to 5.5 V
–
1.65 V to 2.2 V –
–0.2
–
0.4
V
4.5 V to 5.5 V
–
–0.5
–
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–1.0
–
+1.0
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
A
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), and
VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
8. This parameter is guaranteed by design and is not tested.
9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
Document Number: 001-84771 Rev. *K
Page 5 of 20
CY62168G/CY62168GE MoBL
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter
ICC
ISB1
Description
ISB2[10]
45 ns/55 ns
Unit
Min
Typ [7]
Max
f = 22.22 MHz
(45 ns)
–
29.0
36.0
f = 18.18 MHz
(55 ns)
–
29.0
32.0
mA
f = 1 MHz
–
7.0
9.0
mA
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V,
CMOS inputs;
VIN > VCC – 0.2 V, VIN < 0.2 V,
VCC = 4.5 V to 5.5 V
f = fmax (address and data only),
–
5.5
16.0
A
Automatic power down current – f = 0 (OE, and WE), V = V
CC
CC(max)
CMOS inputs; VCC = 1.65 to 2.2 V
–
7
26.0
A
Automatic power down current – CE1 > VCC – 0.2 V or 25 °C [11]
CMOS inputs;
CE2 < 0.2 V,
40 °C [11]
VCC = 4.5 V to 5.5 V
VIN > VCC – 0.2 V or 70 °C [11]
VIN < 0.2 V,
85 °C
f = 0, VCC = VCC(max)
–
5.5
6.5
A
–
6.3
8.0
A
VCC operating supply current
[10]
Test Conditions
VCC = Max,
IOUT = 0 mA,
CMOS levels
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V,
CMOS inputs;
VIN > VCC – 0.2 V or VIN < 0.2 V,
VCC = 1.65 to 2.2 V
mA
mA
–
8.4
12.0
A
–
12.0 [11]
16.0
A
–
7.0
26.0
A
f = 0, VCC = VCC(max)
Notes
10. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
11. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-84771 Rev. *K
Page 6 of 20
CY62168G/CY62168GE MoBL
Capacitance
Parameter [12]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA Unit
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
31.50
°C/W
15.75
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
OUTPUT
R1
VHIGH
GND
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.8
1.2
1.75
1.77
V
VHIGH
1.8
2.5
3.0
5.0
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-84771 Rev. *K
Page 7 of 20
CY62168G/CY62168GE MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR[14, 15]
Data retention current
Conditions
Min
Typ[13]
Max
Unit
1.0
–
–
V
–
7.0
26.0
A
–
5.5
16.0
A
0
–
–
–
45/55
–
–
ns
1.2 V < VCC < 2.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
4.5 V < VCC < 5.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR
[16]
Chip deselect to data retention
time
tR[16, 17]
Operation recovery time
Data Retention Waveform
Figure 4. Data Retention Waveform
V CC
V C C (m in )
tCD R
D A T A R E T E N T IO N M O D E
V D R = 1 . 0 V
V C C (m in )
tR
CE1
(o r)
CE2
Notes
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), and
VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
14. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
15. ICCDR is guaranteed only after device is first powered up to VCC(min) and brought down to VDR.
16. These parameters are guaranteed by design.
17. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-84771 Rev. *K
Page 8 of 20
CY62168G/CY62168GE MoBL
Switching Characteristics
Parameter [18, 19]
45 ns
Description
55 ns
Unit
Min
Max
Min
Max
45.0
–
55.0
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid / Address to ERR valid
tOHA
Data hold from address change / ERR hold from
address change
tACE
tDOE
–
45.0
–
55.0
ns
10.0
–
10.0
–
ns
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
valid
–
45.0
–
55.0
ns
OE LOW to data valid / OE LOW to ERR valid
–
22.0
–
25.0
ns
5.0
–
5.0
–
ns
–
18.0
–
18.0
ns
10.0
–
10.0
–
ns
–
18.0
–
18.0
ns
[19, 20]
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z [19, 20, 21]
CE1 LOW and CE2 HIGH to Low Z
[19, 20]
tHZCE
CE1 HIGH and CE2 LOW to High Z
[19, 20, 21]
tPU[22]
tPD[22]
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
ns
CE1 HIGH and CE2 LOW to power-down
–
45.0
–
55.0
ns
tLZCE
Write
Cycle[23, 24]
tWC
Write cycle time
45.0
–
55.0
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35.0
–
40.0
–
ns
tAW
Address setup to write end
35.0
–
40.0
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35.0
–
40.0
–
ns
tSD
Data setup to write end
25.0
–
25.0
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18.0
–
20.0
ns
10.0
–
10.0
–
ns
tHZWE
tLZWE
WE LOW to High Z
[19, 21, 20]
WE HIGH to Low Z
[19, 20]
Notes
18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified
otherwise.
19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
20. Tested initially and after any design or process changes that may affect these parameters.
21. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
22. These parameters are guaranteed by design and are not tested.
23. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
24. The minimum write cycle pulse width for write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of tHZWE and tSD.
Document Number: 001-84771 Rev. *K
Page 9 of 20
CY62168G/CY62168GE MoBL
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY62168G (Address Transition Controlled)[25, 26]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 6. Read Cycle No. 1 of CY62168GE (Address Transition Controlled)[25, 26]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
25. The device is continuously selected. OE = VIL, CE = VIL.
26. WE is HIGH for read cycle.
Document Number: 001-84771 Rev. *K
Page 10 of 20
CY62168G/CY62168GE MoBL
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled)[27, 28, 29]
ADDRESS
tRC
CE
tPD
t HZCE
tACE
OE
t HZOE
t DOE
t LZOE
DATA I /O
HIGH IMPEDANCE
DATAOUT VALID
HIGH
IMPEDANCE
t LZCE
VCC
SUPPLY
CURRENT
tPU
ISB
Notes
27. WE is HIGH for read cycle.
28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
29. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-84771 Rev. *K
Page 11 of 20
CY62168G/CY62168GE MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled)[30, 31, 32]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
OE
tH Z O E
D A T A I/O
Note 33
tH D
tS D
D A T A I N V A L I D
Notes
30. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
31. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
32. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH.
33. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-84771 Rev. *K
Page 12 of 20
CY62168G/CY62168GE MoBL
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (WE Controlled, OE Low)[34, 35, 36, 37]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
t PWE
WE
tSD
t HZWE
DATA I/O
Note 38
t LZWE
tHD
DATAIN VALID
Figure 10. Write Cycle No. 3 (CE Controlled)[34, 35, 36]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
t PWE
WE
OE
t HZOE
DATA I/O
Note 38
tHD
tSD
DATAIN VALID
Notes
34. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
35. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
36. Data I/O is in high impedance state if CE = VIH, or OE = VIH.
37. The minimum write cycle pulse width should be equal to the sum of the tHZWE and tSD.
38. During this period I/O are in the output state. Do not apply input signals.
Document Number: 001-84771 Rev. *K
Page 13 of 20
CY62168G/CY62168GE MoBL
Truth Table – CY62168G/CY62168GE
CE1
H
CE2
WE
[39]
[39]
X
X
I/Os
Mode
Power
[39]
High Z
Deselect/Power down
Standby (ISB2)
[39]
High Z
Deselect/Power down
Standby (ISB2)
X
[39]
L
L
H
H
L
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
H
High Z
Output disabled
Active (ICC)
L
H
L
X
Data In (I/O0–I/O7)
Write
Active (ICC)
X
[39]
OE
X
X
ERR Output – CY62168GE
Output[40]
Mode
0
Read Operation, no single-bit error in the stored data.
1
Read Operation, single-bit error detected and corrected.
High Z
Device deselected/Outputs disabled/Write Operation.
Note
39. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
40. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-84771 Rev. *K
Page 14 of 20
CY62168G/CY62168GE MoBL
Ordering Information
Speed
(ns)
55
Ordering Code
CY62168G18-55BVXI
Package
Diagram
Package Type (all Pb-free)
51-85150 48-ball VFBGA
Operating
Range
Industrial
48-ball VFBGA, Tape and Reel
CY62168G18-55BVXIT
Ordering Code Definitions
CY 621
6
8
G
X
XX - XX
BV X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
BV = 48-ball VFBGA
Speed Grade: XX = 45
45 = 45 ns
Voltage Range: XX = 18
18 = 1.8 V typ
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: G = 65 nm
Bus Width: 8 = × 8
Density: 6 = 16-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-84771 Rev. *K
Page 15 of 20
CY62168G/CY62168GE MoBL
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 001-84771 Rev. *K
Page 16 of 20
CY62168G/CY62168GE MoBL
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
A
microampere
SRAM
Static Random Access Memory
s
microsecond
VFBGA
Very Fine-Pitch Ball Grid Array
mA
milliampere
WE
Write Enable
mm
millimeter
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-84771 Rev. *K
Symbol
Unit of Measure
Page 17 of 20
CY62168G/CY62168GE MoBL
Document History Page
Document Title: CY62168G/CY62168GE MoBL, 16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-84771
Rev.
ECN No.
Submission
Date
*G
4800984
07/31/2015
Changed status from Preliminary to Final.
*H
5449003
11/03/2016
Updated Maximum Ratings:
Updated Note 5 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding to Operating
Range “2.7 V to 3.6 V”.
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding to Operating
Range “2.2 V to 2.7 V”.
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
*I
6003639
12/22/2017
Updated Cypress Logo and Copyright.
*J
6673157
09/25/2019
Updated Product Portfolio:
Added Note “This device is offered with improved ICC, ISB1 and ISB2 specifications compared
to the current revision with same marketing part number. The new device will be in
production from WW1952. For more information, please contact Cypress sales
representative.” and referred the same note in “CY62168G(E)30”.
Added Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in “CY62168G(E)30”.
Updated DC Electrical Characteristics:
Added Note “This device is offered with improved ICC, ISB1 and ISB2 specifications compared
to the current revision with same marketing part number. The new device will be in
production from WW1952. For more information, please contact Cypress sales
representative.” and referred the same note in ICC, ISB1, ISB2 parameters.
Added Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in ICC, ISB1, ISB2 parameters.
Updated Data Retention Characteristics:
Added Note “This device is offered with improved ICC, ISB1 and ISB2 specifications compared
to the current revision with same marketing part number. The new device will be in
production from WW1952. For more information, please contact Cypress sales
representative.” and referred the same note in ICCDR parameter.
Added Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in ICCDR parameter.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
Document Number: 001-84771 Rev. *K
Description of Change
Page 18 of 20
CY62168G/CY62168GE MoBL
Document History Page (continued)
Document Title: CY62168G/CY62168GE MoBL, 16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-84771
Rev.
ECN No.
Submission
Date
Description of Change
*K
6816924
02/26/2020
Removed CY62168G(E)30 part related information in all instances across the document.
Removed 2.2 V to 3.6 V Voltage Range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
Document Number: 001-84771 Rev. *K
Page 19 of 20
CY62168G/CY62168GE MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-84771 Rev. *K
Revised February 26, 2020
Page 20 of 20
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