CY6264-55SC

1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. Functional Description The CY6264 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. Both devices have an automatic power-down feature (CE1), reducing the power consumption by Logic Block Diagram Pin Configuration SOIC Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 CY6264-2 I/O0 INPUT BUFFER I/O1 A1 A2 A3 A4 A5 A6 A7 A8 I/O2 I/O3 256 x 32 x 8 ARRA Y I/O4 I/O5 I/O6 CE1 CE2 WE OE CY6264-1 COLUMN DECODER POWER DOWN I/O7 Selection Guide CY6264-55 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Shaded area contains advanced information. CY6264-70 70 100 20/15 55 100 20/15 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 1994 – Revised June 1996 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ............................................ –0.5V to +7.0V DC Input Voltage[1]......................................... –0.5V to +7.0V CY6264 Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range 6264-55 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 > VIH, Min. Duty Cycle=100% Max. VCC, CE1 > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Input Load Current Output Leakage Current Output Short Circuit Current[2] VCC Operating Supply Current Automatic CE1 Power–Down Current Automatic CE1 Power–Down Current Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC 0.8 +5 +5 –300 100 20 15 2.2 –0.5 –5 –5 Max. 6264-70 Min. 2.4 0.4 VCC 0.8 +5 +5 –300 100 20 15 Max. Unit V V V V µA µA mA mA mA mA Shaded area contains advanced information. Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 7 Unit pF pF Notes: 1. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns. 2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R1 481Ω 5V OUTPUT R2 255Ω 5 pF INCLUDING JIG AND SCOPE R1 481Ω ALL INPUT PULSES 3.0V R2 255Ω GND 10% 90% 90% 10% < 5 ns CY6264-4 < 5 ns (a) (b) CY6264-3 THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V 2 PRELIMINARY Switching Characteristics Over the Operating Range[4] 6264-55 Parameter READ CYCLE tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD WRITE tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE CYCLE[7] Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[5] 5 WE HIGH to Low Z 50 40 30 40 0 0 25 25 0 20 5 70 60 50 55 0 0 40 35 0 30 Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5] 5 3 20 0 25 0 30 CE1 LOW to Low Z[6] CE2 HIGH to Low Z CE1 HIGH to High CE2 LOW to High Z Z[5, 6] 3 20 5 5 30 5 55 40 25 5 30 55 55 5 70 70 35 70 70 Description Min. Max. Min. 6264-70 CY6264 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE1 LOW to Power-Up CE1 HIGH to Power-Down Shaded area contains advanced information. Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 p F as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 7. The internal write time of the memory is defined by the overlap of CE 1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 3 PRELIMINARY Switching Waveforms Read Cycle No.1[8, 9] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID CY6264 CY6264-5 Read Cycle No. 2 [10, 11] CE1 tRC CE2 OE OE tACE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD ICC 50% ISB CY6264-6 HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (WE Controlled)[9, 11] tWC ADDRESS tSCE1 CE1 CE2 tSCE2 OE tAW WE tSA tPWE tHA tSD DATA IN DATAIN VALID tHZWE DATA I/O DATA UNDEFINED tHD tLZWE HIGH IMPEDANCE CY6264-7 Notes: 8. Device is continuously selected. OE, CE = V IL. CE 2 = VIH. 9. Address valid prior to or coincident with CE transition LOW. 10. WE is HIGH for read cycle. 11. Data I/O is High Z if OE = VIH, CE1 = V IH, or WE = V IL. 4 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [9, 11, 12] tWC ADDRESS CE1 tSA CE2 tSCE2 tAW tPWE WE tSD DATA IN DATAIN VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED tHD tHA tSCE1 CY6264 CY6264-8 Note: 12. If CE g oes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 0.8 0.6 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 0.4 0.2 0.0 −55 ISB 25 125 VCC =5.0V VIN =5.0V 60 40 20 0 0.0 1.0 2.0 3.0 4.0 ICC 0.8 1.2 1.0 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 ICC VCC =5.0V TA =25°C SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.2 1.1 TA =25°C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 0.8 0.6 −55 1.0 1.6 1.4 AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 140 120 100 80 60 VCC =5.0V 40 20 25 125 0 0.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC =5.0V TA =25°C 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) 5 PRELIMINARY CY6264 Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC =4.5V TA =25°C 0.75 1.00 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 VCC =5.0V TA =25°C VCC =0.5V NORMALIZED ICC vs. CYCLE TIME 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE(V) CAPACITANCE(pF) CYCLE FREQUENCY (MHz) Truth Table CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Input/Output High Z High Z Data Out Data In High Z Deselect Read Write Deselect Mode Deselect/Power-Down Address Designators Address Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 Address Function X3 X4 X5 X6 X7 Y1 Y4 Y3 Y0 Y2 X0 X1 X2 Pin Number 2 3 4 5 6 7 8 9 10 21 23 24 25 6 PRELIMINARY Ordering Information Speed (ns) 55 70 55 70 Ordering Code CY6264-55SC CY6264-70SC CY6264-55SNC CY6264-70SNC Package Name S23 S23 S22 S22 Package Type 28-Lead 330-Mil SOIC[13] 28-Lead 330-Mil SOIC 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC [13] CY6264 Operating Range Commercial Commercial Commercial Commercial Shaded area contains advanced information. Note: 13. Not recommended for new designs. Document #: 38-00425-A Package Diagrams 28-Lead 450-Mil (300-Mil Body Width) SOIC S22 7 PRELIMINARY Package Diagrams (continued) 28-Lead (330-Mil) SOIC S23 CY6264 © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.