CY7B993V_11

RoboClock CY7B993V, CY7B994V High Speed Multi Phase PLL Clock Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems. These devices feature a guaranteed maximum TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. Eighteen configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks. Banks 1 to 4 of four outputs allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One of the output banks also includes an independent clock invert function. The feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12 and limited phase adjustments. Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature that allows smooth change-over to secondary clock source, when the primary clock source is not in operation. The reference inputs and feedback inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout. 500 ps Max Total Timing Budget (TTB™) window 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation Matched Pair Output Skew < 200 ps Zero Input-to-Output Delay 18 LVTTL Outputs Driving 50 Terminated Lines 16 Outputs at 200 MHz: Commercial Temperature 6 Outputs at 200 MHz: Industrial Temperature 3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable Reference Inputs Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns Multiply/Divide Ratios of 1–6, 8, 10, 12 Individual Output Bank Disable Output High Impedance Option for Testing Purposes Fully Integrated Phase Locked Loop (PLL) with Lock Indicator 1100V (per MIL-STD-883, Method 3015) Latch up Current................................................... > ±200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C –40C to +85C VCC 3.3V 10% 3.3V 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK) LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1] VCC = Min, IOH = –30 mA 2.4 VOH LOCK IOH = –2 mA, VCC = Min 2.4 LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1] VCC = Min, IOL= 30 mA – VOL – LOCK IOL= 2 mA, VCC = Min IOZ High impedance State Leakage Current –100 LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4]) LVTTL Input HIGH FBK[A:B]±, REF[A:B]± Min < VCC < Max 2.0 VIH REFSEL, FBSEL, FBDIS, 2.0 DIS[1:4] VIL LVTTL Input LOW FBK[A:B]±, REF[A:B]± Min < VCC < Max –0.3 REFSEL, FBSEL, FBDIS, DIS[1:4] –0.3 LVTTL VIN >VCC FBK[A:B]±, REF[A:B]± VCC = GND, VIN = 3.63V – II LVTTL Input HIGH FBK[A:B]±, REF[A:B]± VCC = Max, VIN = VCC – IlH Current REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC – LVTTL Input LOW FBK[A:B]±, REF[A:B]± VCC = Max, VIN = GND –500 IlL Current REFSEL, FBSEL, FBDIS, DIS[1:4] –500 Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST)) Three-level Input HIGH[6] Min < VCC < Max 0.87*VCC VIHH Three-level Input MID[6] Min < VCC < Max 0.47*VCC VIMM [6] Three-level Input LOW Min < VCC < Max – VILL Three-level Input Three-level input pins excl. FBF0 VIN = VCC – IIHH HIGH Current FBF0 – Three-level Input Three-level input pins excl. FBF0 VIN = VCC/2 –50 IIMM MID Current FBF0 –100 Three-level Input Three-level input pins excl. FBF0 VIN = GND –200 IILL LOW Current FBF0 –400 LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±) Input Differential Voltage 400 VDIFF Highest Input HIGH Voltage 1.0 VIHHP Lowest Input LOW Voltage GND VILLP Common Mode Range (crossing voltage) 0.8 VCOM Max – – 0.5 0.5 100 VCC + 0.3 VCC + 0.3 0.8 0.8 100 500 500 – – – 0.53*VCC 0.13*VCC 200 400 50 100 – – VCC VCC VCC – 0.4 VCC Unit V V V V A V V V V A A A A A V V V A A A A A A mV V V V Notes 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. Document #: 38-07127 Rev. *J Page 10 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Electrical Characteristics Over the Operating Range Parameter Description Operating Current Internal Operating ICCI Current ICCN Output Current Dissipation/Pair[8] CY7B993V CY7B994V CY7B993V CY7B994V (continued) Test Conditions VCC = Max, fMAX[7] VCC = Max, CLOAD = 25 pF, RLOAD = 50 at VCC/2, fMAX Min – – – – Max 250 250 40 50 Unit mA mA mA mA Capacitance Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Min – Max 5 Unit pF Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] Parameter fIN fOUT tSKEWPR tSKEWBNK tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEWCPR tCCJ1-3 tCCJ4-12 tPD Clock Input Frequency Clock Output Frequency Matched-Pair Skew[14, 15] Intrabank Skew[14, 15] Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[14, 15] Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[14, 15] Output-Output Skew (invert to nominal of different banks, compared banks at same frequency, rising edge to falling edge aligned, other banks at same frequency)[14, 15] Output-Output Skew (all output configurations outside of tSKEW1and tSKEW2)[14, 15] Complementary Outputs Skew (crossing to crossing, complementary outputs of the same bank)[14, 15, 16, 17] Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) Propagation Delay, REF to FB Rise Description CY7B993V CY7B994V CY7B993V CY7B994V CY7B993/4V-2 Min 12 24 12 24 – – – – – Typ – – – – – – – – – Max 100 200 100 200 200 200 250 250 250 CY7B993/4V-5 Min 12 24 12 24 – – – – – Typ – – – – – – – – – Max 100 200 100 200 200 250 550 650 700 Unit MHz MHz MHz MHz ps ps ps ps ps – – – – –250 – – 50 50 – 500 200 150 100 250 – – – – –500 – – 50 50 – 800 300 150 100 500 ps ps ps Peak ps Peak ps Notes 7. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 200 MHz for CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50 at VCC/2. 9. This is for non-three level inputs. 10. Assumes 25 pF Max load capacitance up to 185 MHz. At 200 MHz the Max load is 10 pF. 11. Both outputs of pair must be terminated, even if only one is being used. 12. Each package must be properly decoupled. 13. AC parameters are measured at 1.5V unless otherwise indicated. 14. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz. 15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 16. Complementary output skews are measured at complementary signal pair intersections. 17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-07127 Rev. *J Page 11 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] (continued) Parameter TTB tPDDELTA tREFpwh tREFpwl tr/tf tLOCK tRELOCK1 tRELOCK2 tODCV tPWH tPWL tPDEV tOAZ tOAZ 18] Description Total Timing Budget window (same frequency and phase)[17, CY7B993/4V-2 Min – – 2.0 2.0 0.15 – – – –1.0 – – – 1.0 0.5 Typ – – – – – – Max 500 200 – – 2.0 10 500 1000 1.0 1.5 2.0 0.025 10 14 CY7B993/4V-5 Min – – 2.0 2.0 0.15 – – – –1.0 – – – 1.0 0.5 Typ – – – – – – Max 700 200 – – 2.0 10 500 1000 1.0 1.5 2.0 0.025 10 14 Unit ps ps ns ns ns ms s s ns ns ns UI ns ns Propagation Delay difference between two devices[17] REF input (Pulse Width HIGH)[19] REF input (Pulse Width LOW)[19] Output Rise/Fall Time[20] PLL Lock Time from Power up PLL Relock Time (from same frequency, different phase) with Stable Power Supply PLL Relock Time (from different frequency, different phase) with Stable Power Supply[21] Output duty cycle deviation from 50%[13] Output HIGH time deviation from 50%[22] Output LOW time deviation from 50%[22] Period deviation when changing from reference to reference[23] DIS[1:4]/FBDIS HIGH to output high impedance from ACTIVE[14, 24] DIS[1:4]/FBDIS LOW to output ACTIVE from output high impedance [24, 25] Figure 5. AC Test Loads and Waveform[26] 3.3V For LOCK output only R1 = 910 R2 = 910 CL < 30 pF OUTPUT For all other outputs R1 = 100 CL R2 = 100 CL < 25 pF to 185 MHz or 10 pF at 200 MHz (Includes fixture and probe capacitance) R1 R2 (a) LVTTL AC Test Load 3.3V GND < 1 ns 2.0V 0.8V 2.0V 0.8V < 1 ns (b) TTL Input Test Waveform Notes 18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given frequency. 19. Tested initially and after any design or process changes that may affect these parameters. 20. Rise and fall times are measured between 2.0V and 0.8V. 21. fNOM must be within the frequency range defined by the same FS state. 22. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period. 24. Measured at 0.5V deviation from starting voltage. 25. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz. 26. These figures are for illustrations only. The actual ATE loads may vary. Document #: 38-07127 Rev. *J Page 12 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V AC Timing Diagrams[13] tREFpwl tREFpwh REF tPD t PWH 2.0V FB 0.8V tCCJ1-3,4-12 Q [1:4]QA[0:1] t SKEWBNK REF TO DEVICE 1 and 2 [1:4]QB[0:1] tODCV tPD FB DEVICE1 tPDELTA FB DEVICE2 tPDELTA Q t SKEW0,1 Other Q t SKEW0,1 t SKEWBNK t PWL QFA0 or [1:4]Q[A:B]0 t SKEWPR QFA1 or [1:4]Q[A:B]1 t SKEWPR tODCV tSKEWCPR Q tSKEW2 INVERTED Q tSKEW2 COMPLEMENTARY A crossing COMPLEMENTARY B crossing Document #: 38-07127 Rev. *J Page 13 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Ordering Information Propagation Delay (ps) 250 250 500 500 Pb-free 250 250 250 250 250 250 250 250 250 250 250 500 500 500 500 500 500 500 500 500 500 100 100 100 200 200 200 200 200 200 200 200 100 100 100 100 200 200 200 200 200 200 CY7B993V-2AXC CY7B993V-2AXCT CY7B993V-2AXI CY7B994V-2AXC CY7B994V-2AXCT CY7B994V-2BBXC CY7B994V-2BBXCT CY7B994V-2AXI CY7B994V-2AXIT CY7B994V-2BBXI CY7B994V-2BBXIT CY7B993V-5AXC CY7B993V-5AXCT CY7B993V-5AXI CY7B993V-5AXIT CY7B994V-5AXC CY7B994V-5AXCT CY7B994V-5BBXI CY7B994V-5BBXIT CY7B994V-5AXI CY7B994V-5AXIT 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel 100-Ball Thin Ball Grid Array 100-Ball Thin Ball Grid Array - Tape and Reel 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel 100-Ball Thin Ball Grid Array 100-Ball Thin Ball Grid Array -Tape and Reel 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel 100-Ball Thin Ball Grid Array 100-Ball Thin all Grid Array - Tape and Reel 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack - Tape and Reel Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Max Speed (MHz) 200 200 200 200 Ordering Code CY7B994V-2BBI CY7B994V-2BBIT CY7B994V-5BBC CY7B994V-5BBCT Package Type 100-Ball Thin Ball Grid Array 100-Ball Thin Ball Grid Array -Tape and Reel 100-Ball Thin Ball Grid Array 100-Ball Thin Ball Grid Array - Tape and Reel Operating Range Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Ordering Code Definitions CY 7B99XV - X XX X X T T = Tape and Reel, Blank = Standard Temperature Range C = Commercial = 0 °C to 70 °C I = Industrial = –40 °C to 85 °C X = Pb-free indicator (blank = leaded) Package Type: A = Thin Quad Flat Pack; BB = Thin Ball Grid Array Propagation delay: 2 = 250 ps max; 5 = 500 ps max Base part number Company ID: CY = Cypress Document #: 38-07127 Rev. *J Page 14 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Package Diagrams Figure 6. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048 *E Document #: 38-07127 Rev. *J Page 15 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Package Diagrams (continued) Figure 7. 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107 *C Document #: 38-07127 Rev. *J Page 16 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Document History Page Document Title: RoboClock CY7B993V/CY7B994V High speed Multi Phase PLL Clock Buffer Document Number: 38-07127 Revision ** *A *B *C *D ECN 109957 114376 116570 122794 123694 Orig. of Change SZV CTK HWT RBI RGL Submission Date 12/16/01 05/06/02 09/04/02 12/14/02 03/04/03 Description of Change Changed from Spec number: 38-00747 to 38-07127 Added three industrial packages Added TTB Features Power up requirements to operating conditions information Added Min Fout value of 12 MHz for CY7B993V and 24 MHz for CY7B994V to switching characteristics table Corrected prop delay limit parameter from (tPDSL,M,H) to tPD in the Lock Detect Output Description paragraph Added clock input frequency (fin) specifications in the switching characteristics table Added Lead-free devices Added typical values for jitter Changed “Lead-Free” to “Pb-Free” in Ordering Information table. Removed obsolete part numbers: CY7B993V-2AC, CY7B993V-2ACT, CY7B993V-2AI, CY7B993V-2AIT, CY7B994V-2AC, CY7B994V-2ACT, CY7B994V-2BBCT, CY7B994V-2AI, CY7B994V-2AIT, CY7B993V-5AC, CY7B993V-5ACT, CY7B993V-5AI, CY7B993V-5AIT, CY7B994V-5AC, CY7B994V-5ACT, CY7B994V-5BBI, CY7B994V-5BBIT, CY7B994V-5AI, CY7B994V-5AIT and CY7B993V-2AXIT Added numerical temperature ranges to Ordering Information table Removed Part number CY7B994V-5BBXC and CY7B994V-5BBXCT. Added Ordering Code Definitions. Updated Ordering Code Definitions. Updated minimum Storage Temperature and 100-pin TQFP package diagram *E *F *G 128462 391560 2896548 RGL RGL KVM 07/29/03 See ECN 03/19/10 *H *I *J 3055192 3076912 3240908 CXQ CXQ CXQ 10/11/2010 11/02/2010 04/26/2011 Document #: 38-07127 Rev. *J Page 17 of 18 [+] Feedback RoboClock CY7B993V, CY7B994V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07127 Rev. *J ® ® Revised April 26, 2011 Page 18 of 18 TTB™ is a trademark and RoboClock and PSoC are the registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. [+] Feedback