CY7C09349AV-12AXCT

CY7C09359AV3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM CY7C09349AV CY7C09359AV 3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM 3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM Features ■ 3.3 V low operating power ❐ Active = 135 mA (typical) ❐ Standby = 10 µA (typical) ■ Fully synchronous interface for easier operation ■ Burst counters increment addresses internally ❐ Shorten cycle times ❐ Minimize bus noise ❐ Supported in flow-through and pipelined modes ■ True dual ported memory cells which allow simultaneous access of the same memory location ■ Two flow-through/pipelined devices ❐ 4 K × 18 organization (CY7C09349AV) ❐ 8 K × 18 organization (CY7C09359AV) ■ Three modes ❐ Flow-through ❐ Pipelined ❐ Burst ■ Dual chip enables for easy depth expansion ■ Upper and lower byte controls for bus matching ■ Pipelined output mode on both ports allows fast 83-MHz operation ■ Automatic power-down 0.35-micron CMOS for optimum speed/power ■ Commercial and industrial temperature ranges ■ High-speed clock to data access 9 and 12 ns (max) ■ Available in 100-pin TQFP ■ Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL 1 CE0R CE1R LBR 1 0 0 0/1 0/1 OEL OER FT/PipeL 0/1 1b 0b 1a 0a b 0a 1a 0b 1b a a b 9 9 I/O9L–I/O17L [1] A0L–A11/12L CLKL ADSL CNTENL CNTRSTL I/O Control 9 I/O0L–I/O8L FT/PipeR 0/1 I/O9R–I/O17R I/O Control 9 12/13 I/O0R–I/O8R 12/13 Counter/ Address Register Decode Counter/ Address Register Decode True Dual Ported RAM Array [1] A0R–A11/12R CLKR ADSR CNTENR CNTRSTR Note 1. A0–A11 for 4 K; A0–A12 for 8 K devices. Cypress Semiconductor Corporation Document Number: 001-63888 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 28, 2010 [+] Feedback CY7C09349AV CY7C09359AV Functional Description The CY7C09349AV and CY7C09359AV are high-speed 3.3 V synchronous CMOS 4 K and 8 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[2] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple chip enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s address strobe (ADS). When the port’s count enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin thin quad plastic flatpack (TQFP) packages. Note 2. When simultaneously writing to the same location, final value cannot be guaranteed. Document Number: 001-63888 Rev. ** Page 2 of 20 [+] Feedback CY7C09349AV CY7C09359AV Contents Pin Configuration ............................................................. 4 Selection Guide ................................................................ 4 Pin Definitions .................................................................. 5 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 6 Capacitance ...................................................................... 6 AC Test Loads .................................................................. 7 Switching Characteristics ................................................ 8 Document Number: 001-63888 Rev. ** Switching Waveforms ...................................................... 9 Read/Write and Enable Operation ................................. 16 Address Counter Control Operation ............................. 16 Ordering Information ...................................................... 17 Package Diagram ............................................................ 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 20 Page 3 of 20 [+] Feedback CY7C09349AV CY7C09359AV Pin Configuration A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 1. 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A8R A10L 2 74 A9R A11L 3 73 A10R [3] A12L 4 72 NC 5 71 A11R [3] A12R NC 6 70 NC NC 7 69 NC NC LBL 8 68 UBL 9 67 LBR CE0L 10 66 UBR CE1L 11 CNTRSTL 12 R/WL 13 OEL 14 VCC CY7C09359AV (8 K × 18) 65 CE0R 64 CE1R 63 CNTRSTR 62 R/WR 15 61 GND FT/PIPEL 16 60 OER I/O17L 17 59 FT/PIPER I/O16L 18 58 I/O17R GND 19 57 GND I/O15L 20 56 I/O16R I/O14L 21 55 I/O15R I/O13L 22 54 I/O14R 1/012L 23 53 I/O13R I/O11L 24 52 I/O12R I/O10L 25 51 I/O11R CY7C09349AV (4 K × 18) I/10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C09349AV CY7C09359AV –9 CY7C09349AV CY7C09359AV –12 fMAX2 (MHz) (pipelined) 67 50 Max access time (ns) (clock to data, pipelined) 9 12 Typical operating current ICC (mA) 135 115 Typical standby current for ISB1 (mA) (both ports TTL level) 20 20 10 µA 10 µA Typical standby current for ISB3 (µA) (both ports CMOS level) Note 3. This pin is NC for CY7C09349AV. Document Number: 001-63888 Rev. ** Page 4 of 20 [+] Feedback CY7C09349AV CY7C09359AV Pin Definitions Left Port Right Port Description A0L–A12L A0R–A12R Address inputs (A0–A11 for 4 K, A0–A12 for 8 K devices). ADSL ADSR Address strobe input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. CE0L, CE1L CE0R, CE1R Chip enable input. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0  VIL and CE1 VIH). CLKL CLKR Clock signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter enable input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter reset input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O17L I/O0R–I/O17R Data bus input/output (I/O0–I/O15 for ×16 devices). LBL LBR Lower byte select input. Asserting this signal LOW enables read and write operations to the lower byte (I/O0–I/O8 for ×18, I/O0–I/O7 for ×16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. UBL UBR Upper byte select input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L). OEL OER Output enable input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/write enable input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow-through/pipelined select input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground input. NC No connect. VCC Power input. Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature................................ –65 C to +150 C Ambient temperature with power applied . –55 C to +125 C Supply voltage to ground potential ...............–0.5 V to +4.6 V DC voltage applied to outputs in high Z state ......................... –0.5 V to VCC + 0.5 V DC input voltage .................................. –0.5 V to VCC + 0.5 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001 V Latch-up current ..................................................... > 200 mA Operating Range Range Ambient Temperature VCC Commercial 0 C to +70 C 3.3 V ± 300 mV Industrial[4] –40 C to +85 C 3.3 V ± 300 mV Note 4. Industrial parts are available in CY7C09359AV only. Document Number: 001-63888 Rev. ** Page 5 of 20 [+] Feedback CY7C09349AV CY7C09359AV Electrical Characteristics Over the Operating Range CY7C09349AV CY7C09359AV Parameter Description –9 Unit –12 Min Typ Max Min Typ Max VOH Output HIGH voltage (VCC = Min, IOH = –4.0 mA) 2.4 – – 2.4 – – V VOL Output LOW voltage (VCC = Min, IOH = +4.0 mA) – 0.4 – 0.4 V VIH Input HIGH voltage 2.0 – 2.0 – V VIL Input LOW voltage – 0.8 – 0.8 V IOZ Output leakage current –10 10 –10 10 µA ICC Operating current (VCC = Max, IOUT = 0 mA) outputs disabled 230 – 115 180 mA 155 250 mA 20 70 mA 30 80 mA 85 140 mA 95 150 mA 10 500 µA 10 500 µA 75 100 mA 85 110 mA ISB1 ISB2 ISB3 ISB4 Commercial Standby current (both ports TTL CEL and CER  VIH, f = fMAX Standby current (one port TTL CEL or CER  VIH, f = fMAX – 135 Industrial[5] level)[6] Commercial 20 Industrial[5] level)[6] CEL and CER  VCC – 0.2 V, f = 0 level)[6] 95 [5] 155 – Commercial 10 Industrial[5] 500 – Commercial Industrial 75 – Commercial Industrial Standby current (both ports CMOS level)[6] Standby current (one port CMOS CEL or CER  VIH, f = fMAX – 85 [5] 115 – Capacitance Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 10 pF 10 pF Notes 5. Industrial parts are available in CY7C09359AV only. 6. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0  VIL and CE1 VIH). Document Number: 001-63888 Rev. ** Page 6 of 20 [+] Feedback CY7C09349AV CY7C09359AV AC Test Loads 3.3 V 3.3 V R1 = 590 OUTPUT C = 30 pF R2 = 435 OUTPUT RTH = 250  R1 = 590 OUTPUT C = 30 pF C = 5 pF VTH = 1.4 V (a) Normal Load (Load 1) Document Number: 001-63888 Rev. ** (b) Thévenin Equivalent (Load 1) R2 = 435 (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) Page 7 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Characteristics Over the Operating Range CY7C09349AV CY7C09359AV –9 Parameter Description –12 Min Max Min Max Unit – 40 – 33 MHz fMAX1 fMax flow-through fMAX2 fMax pipelined – 67 – 50 MHz tCYC1 Clock cycle time – flow-through 25 – 30 – ns tCYC2 Clock cycle time – pipelined 15 – 20 – ns tCH1 Clock HIGH time – flow-through 12 – 12 – ns tCL1 Clock LOW time – flow-through 12 – 12 – ns tCH2 Clock HIGH time – pipelined 6 – 8 – ns tCL2 Clock LOW time – pipelined 6 – 8 – ns tR Clock rise time – 3 – 3 ns tF Clock fall time – 3 – 3 ns tSA Address set-up time 4 – 4 – ns tHA Address hold time 1 – 1 – ns tSC Chip enable set-up time 4 – 4 – ns tHC Chip enable hold time 1 – 1 – ns tSW R/W set-up time 4 – 4 – ns tHW R/W hold time 1 – 1 – ns tSD Input data set-up time 4 – 4 – ns tHD Input data hold time 1 – 1 – ns tSAD ADS set-up time 4 – 4 – ns tHAD ADS hold time 1 – 1 – ns tSCN CNTEN set-up time 4 – 4 – ns tHCN CNTEN hold time 1 – 1 – ns tSRST CNTRST set-up time 4 – 4 – ns tHRST CNTRST hold time 1 – 1 – ns tOE Output enable to data valid – 10 – 12 ns tOLZ OE to low Z 2 – 2 – ns tOHZ OE to high Z 1 7 1 7 ns tCD1 Clock to data valid – flow-through – 20 – 25 ns tCD2 Clock to data valid – pipelined – 9 – 12 ns tDC Data output hold after clock HIGH 2 – 2 – ns tCKHZ Clock HIGH to output high Z 2 9 2 9 ns tCKLZ Clock HIGH to output low Z 2 – 2 – ns Port to port delays tCWDD Write port clock HIGH to read data delay – 40 – 40 ns tCCS Clock to clock set-up time – 15 – 15 ns Document Number: 001-63888 Rev. ** Page 8 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms Read Cycle for Flow-through Output (FT/PIPE = VIL)[7, 8, 9, 10] tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 tCKLZ Qn+2 tDC tOHZ tOLZ OE tOE Read Cycle for Pipelined Operation (FT/PIPE = VIH)[7, 8, 9, 10] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 7. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 8. ADS = VIL, CNTEN and CNTRST = VIH. 9. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. 10. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document Number: 001-63888 Rev. ** Page 9 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms (continued) Bank Select Pipelined Read[11, 12] tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tDC tSC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC CE0(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ tCKLZ Left Port Write to Flow-through Right Port Read[13, 14, 15, 16] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 11. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 12. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 13. The same waveforms apply for a right port write to flow-through left port read. 14. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 15. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 16. If tCCS  maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document Number: 001-63888 Rev. ** Page 10 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[17, 18, 19, 20] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Pipelined Read-to-Write-to-Read (OE Controlled)[17, 18, 19, 20] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W ADDRESS tSW tHW tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAOUT Dn+3 tCD2 DATAIN tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 17. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 18. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 19. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 20. During “No operation”, data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 001-63888 Rev. ** Page 11 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms (continued) Flow-through Read-to-Write-to-Read (OE = VIL)[21, 22, 24, 25] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Flow-through Read-to-Write-to-Read (OE Controlled)[21, 22, 23, 24, 25] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS tSA DATAIN DATAOUT An+1 An+2 tSD tHA An+4 An+5 tHD Dn+2 tDC tCD1 An+3 Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE READ Notes 21. ADS = VIL, CNTEN and CNTRST = VIH. 22. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 23. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 24. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 25. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 001-63888 Rev. ** Page 12 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms (continued) Pipelined Read with Address Counter Advance[26] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn tDC Qn+1 READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Flow-through Read with Address Counter Advance[26] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn+3 Qn+2 COUNTER HOLD READ WITH COUNTER Note 26. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document Number: 001-63888 Rev. ** Page 13 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms (continued) Write with Address Counter Advance (Flow-through or Pipelined Outputs)[27, 28] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Notes 27. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 28. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document Number: 001-63888 Rev. ** Page 14 of 20 [+] Feedback CY7C09349AV CY7C09359AV Switching Waveforms (continued) Counter Reset (Pipelined Outputs)[29, 30, 31, 32] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 29. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 30. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 31. CE0, UB, and LB = VIL; CE1 = VIH. 32. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document Number: 001-63888 Rev. ** Page 15 of 20 [+] Feedback CY7C09349AV CY7C09359AV Read/Write and Enable Operation[33, 34, 35] Inputs OE CLK CE0 Outputs CE1 R/W I/O0–I/O17 Operation [36] X H X X High Z Deselected X X L X High Z Deselected[36] X L H L DIN L L H H DOUT Read[36] L H X High Z Outputs disabled H X Write Address Counter Control Operation[33, 37, 38, 39] Address Previous Address X CLK ADS CNTEN CNTRST I/O Mode Operation X X X L Dout(0) Reset Counter reset to address 0 An X L X H Dout(n) Load Address load into counter X An H H H Dout(n) Hold External address blocked—counter disabled X An H L H Dout(n+1) Increment Counter enabled—internal address generation Notes 33. “X” = “Don’t Care,” “H” = VIH, “L” = VIL. 34. ADS, CNTEN, CNTRST = “Don’t Care.” 35. OE is an asynchronous input signal. 36. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 37. CE0 and OE = VIL; CE1 and R/W = VIH. 38. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 39. Counter operation is independent of CE0 and CE1. Document Number: 001-63888 Rev. ** Page 16 of 20 [+] Feedback CY7C09349AV CY7C09359AV Ordering Information 4 K × 18 3.3 V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 9 CY7C09349AV-9AXC A100 100-pin Pb-free Thin Quad Flat Pack Commercial 12 CY7C09349AV-12AXC A100 100-pin Pb-free Thin Quad Flat Pack Commercial 8 K × 18 3.3 V Synchronous Dual-Port SRAM Speed (ns) 9 Ordering Code CY7C09359AV-9AXC Package Name A100 Package Type 100-pin Pb-free Thin Quad Flat Pack Operating Range Commercial Ordering Code Definitions CY7C 09 XX9 AV - XX AX C Temperature Range: C = Commercial Package Type: AX = 100-pin Thin Quad Flat Pack (Pb-free) Speed Bin: XX = 9 or 12 3.3 V Density: XX9 = 349 or 359 Dual Port SRAM Cypress SRAMs Document Number: 001-63888 Rev. ** Page 17 of 20 [+] Feedback CY7C09349AV CY7C09359AV Package Diagram Figure 2. 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048 *D Document Number: 001-63888 Rev. ** Page 18 of 20 [+] Feedback CY7C09349AV CY7C09359AV Acronyms Document Conventions Acronym Description CE chip enable CLK clock CMOS complementary metal oxide semiconductor I/O Input/output OE output enable SRAM static random access memory TQFP thin quad flat pack Document Number: 001-63888 Rev. ** Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mV milli Volts mW milli Watts MHz Mega Hertz pF pico Farad °C degree Celcius W Watts Page 19 of 20 [+] Feedback CY7C09349AV CY7C09359AV Document History Page Document Title: CY7C09349AV/CY7C09359AV 3.3 V 4 K/8 K × 18 Synchronous Dual-Port Static RAM Document Number: 001-63888 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 2998931 09/16/2010 RAME New Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-63888 Rev. ** Revised September 28, 2010 Page 20 of 20 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback